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<galibert[m]>
Catherine: I wouldn’t put it past some fpgas to be quite silly and have an active-low oe
<whitequark[cis]>
hm? the platform layer handles that
<whitequark[cis]>
and iirc this is true for Xilinx
<galibert[m]>
Oh good
<galibert[m]>
I didn’t realize the platform layer could do some comb
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<gatecat>
it's also true for ECP5
<galibert[m]>
Anyone here has an opinon about the Efinix Titanium Ti180 ?
<galibert[m]>
It's going to be used that this mister-inspired Mars thingy
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<ravenslofty[m]>
The FPGA architecture is a mess, but that's not that much of a surprise
<galibert[m]>
They say it's significantly more powerful that the sx120, I'm not entirely convinced
<ravenslofty[m]>
The math works out a little weird: the "120" bit in Intel's chip is a marketing number to convert LUT6s to LUT4s. As we know, LAB input limits mean there's no way you're packing that much logic into there. On the other hand, Efinix is LUT4, but each LUT4 is either logic or routing, and the constant is bad enough that the marketing number is about 40% *less* than the number of LUTs on the chip
<ravenslofty[m]>
(I'm ill and not quite coherent, I apologise)
<galibert[m]>
logic or routing? I missed that one
<galibert[m]>
oh yeah, xlr cell
<ravenslofty[m]>
It's underprovisioning your routing and selling it as a feature, really
<galibert[m]>
Yeah. I'm sure nextpnr would just love such an architecture
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<mcc111[m]>
Is there a python package that can do arbitrary-width bit rotates? Like if I want to bit rotate on a 30 bit register (I see I can do this on Values but say I want to do it on numbers, say so I can set reset=)
<mcc111[m]>
Yes, this is easy to implement, but I think it's better to reuse rather than implement per-project for basic math
<mcc111[m]>
Alternately, If I say like… Const(30, 0x7).rotate_right(2) … and then I assign that Const to a reset= … will that do what I expect?