whitequark[cis] changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings: Amaranth each Mon 1700 UTC, Amaranth SoC each Fri 1700 UTC · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang · Matrix #amaranth-lang:matrix.org
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<iposthuman[m]> Could someone explain something to me? I'm using an adaptation of @cr1901's PLL code. I thought the default clock domain was called "sync", so i'm confused why this line ```m.domains.sync = ClockDomain("sync")``` is present from this ``` m.domains.sync = ClockDomain("sync")... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/FiaGQDTgVyDyYtxnnEmydPrp>)
<iposthuman[m]> if i leave the first line out i get an error ```File "/home/iposthuman/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py", line 397, in add_defs
<iposthuman[m]> assert defs[sig] is self```
<whitequark[cis]> try replacing ClockSignal("sync") above with a new signal that you then assign to ClockSignal
<iposthuman[m]> i think i'm not understanding what Clockdomain("sync") is ultimately doing. I thought it was adding a *new* domain? yes?
<whitequark[cis]> it does
<whitequark[cis]> oh, wait, I misunderstood what's going on
<whitequark[cis]> disregard the above
<iposthuman[m]> ok
<whitequark[cis]> I think the reason you're hitting the error is that, if you leave out your own clock domain definition, Amaranth creates one for you using the board's default clock and reset
<whitequark[cis]> and because you have multiple drivers for the sync's clock signal, you get a driver-driver conflict for which we do not print a good error message
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<iposthuman[m]> Ah! that makes sense now. I forgot about the board's default. Oops. Thanks @Catherine.
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<_whitenotifier-3> [amaranth-boards] whitequark closed pull request #233: Add support for Tang Nano 9k - https://github.com/amaranth-lang/amaranth-boards/pull/233
<_whitenotifier-3> [amaranth-lang/amaranth-boards] whitequark pushed 1 commit to main [+1/-0/±0] https://github.com/amaranth-lang/amaranth-boards/compare/54000b094980...48239718d050
<_whitenotifier-3> [amaranth-lang/amaranth-boards] whitequark 4823971 - Add support for Tang Nano 9k.
<_whitenotifier-3> [amaranth-boards] whitequark closed pull request #208: Initial support for Tang nano 9k board - https://github.com/amaranth-lang/amaranth-boards/pull/208
<_whitenotifier-3> [amaranth-boards] whitequark commented on pull request #208: Initial support for Tang nano 9k board - https://github.com/amaranth-lang/amaranth-boards/pull/208#issuecomment-1846376855
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<iposthuman[m]> Hmmm. i think i'm missing something basic about clock input pins. My super basic pll test isn't working and fairly sure it is because i haven't connected *things* together at the pin level. This is my simple test: https://github.com/wdevore/Retro-Amaranth/blob/main/Learning/keks/pll/basic.py
<iposthuman[m]> I've seen examples that say and do:```# If you don't specify dir='-', you will experience a world
<iposthuman[m]> # of debugging pain.
<iposthuman[m]> clk_pin = platform.request(platform.default_clk, dir='-')```
<iposthuman[m]> i think i'm missing some sort of pin wiring much like this: ```m.d.comb += [
<iposthuman[m]> pll.clk_pin.eq(clk_pin),```
<iposthuman[m]> my code uses ```clk_frequency = int(platform.default_clk_constraint.frequency)``` which i think is incorrect.
<whitequark[cis]> try i_REFERENCECLK = clk_pin
<iposthuman[m]> ok.
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<iposthuman[m]> I made tweaks but my pll still isn't working: https://github.com/wdevore/Retro-Amaranth/blob/main/Learning/keks/pll/basic.py
<iposthuman[m]> The code is basically an extraction of @cr1901's code. i don't think i'm wiring the pll's output to the "sync" domain correctly?
<whitequark[cis]> that looks correct to me at first glance
<iposthuman[m]> ok. hmmmm
<cr1901> Remind me of my code again?
<cr1901> (Oh God, WHY did they name it KEKs?)
<cr1901> crzwdjk is not me, FWIW :P
<iposthuman[m]> i'm sure it means something in German as it's a German company. 😉
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<iposthuman[m]> i searched my notes and i thought it was you. i'm scanning the chat to see who suggested it.
<whitequark[cis]> crzwdjk, I assume
<iposthuman[m]> the url indicates it but i'm double checking
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<iposthuman[m]> strange i can find a reference to him on the 4th but it isn't about plls
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<iposthuman[m]> it must have been crzwdjk because he responded with:```You need to create an Instance, yes. You can precompute the parameters needed if you just want a fixed frequency, otherwise you would need code to compute them. Here’s the code from my project: https://github.com/crzwdjk/uniterm/blob/main/gateware/icepll.py```
<iposthuman[m]> yet i can't find any of that dialog going back to the 1st *confused*
<whitequark[cis]> sometimes there are issues in the bridging meaning that not everything is logged
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<iposthuman[m]> I found it:```16:18 <iposthuman[m]> It's funny how they integrated their website/company in various files and folders.... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/PWSerUXpKHiqfEDnlcNCMRee>)
<iposthuman[m]> it was the 30th of last month
<iposthuman[m]> The Keks has an HX8K which according to the spec uses SB_PLL40_CORE and not ...PAD
<whitequark[cis]> there are both SB_PLL40_CORE and SB_PLL40_PAD primitives in each device
<whitequark[cis]> they use the same silicon, the only difference is the exact nature of routing
<iposthuman[m]> oh. hmmm
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<iposthuman[m]> I tried PAD and it doesn't work. I've used plls on ecp5 in systemverilog and it worked. it's very possible i've missed some detail somewhere.
<iposthuman[m]> i try tomorrow Zzzz...
<whitequark[cis]> good night
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<iposthuman[m]> chow
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* tpw_rules just completed the world's worst axi target
<galibert[m]> I’m sure Xilinx managed worse
<tpw_rules> also sad news: python+numpy is not a very good systems language and doesn't offer precise control over what types of transactions i get
<whitequark[cis]> transactions?
<tpw_rules> for some reason writing through a uint32 array was causing a byte read in some circumstances
<whitequark[cis]> um
<whitequark[cis]> are you... using numpy to access mmio?
<tpw_rules> maybe
<Darius> ..
<Darius> are you cackling madly while throwing a knife switch?
<galibert[m]> Heard a gasp coming from a general northly direction
<cr1901> This is cursed and I love it
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<whitequark[cis]> wtf
<whitequark[cis]> but yeah, you could actually get the same problem if you use C but omit volatile
<whitequark[cis]> the compiler is allowed to split reads if it so desires
<whitequark[cis]> (this happens if you try to define an MMIO register as a bitfield)
<tpw_rules> i'm mildly sorry
<whitequark[cis]> lol
<whitequark[cis]> it's cool
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<tpw_rules> what docstring format does amaranth use?
<whitequark[cis]> sphinx
<whitequark[cis]> more specifically, one sec
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<tpw_rules> oh, they call it numpy style
<tpw_rules> funny how everything comes full circle :)
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<_whitenotifier-3> [yosys] whitequark created branch npmjs - https://github.com/YoWASP/yosys
<_whitenotifier-3> [yosys] whitequark opened pull request #28: Add experimental JavaScript package - https://github.com/YoWASP/yosys/pull/28
<_whitenotifier-3> [yosys] whitequark commented on issue #21: Browser package (npm) - https://github.com/YoWASP/yosys/issues/21#issuecomment-1846786174
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<_whitenotifier-3> [yosys] whitequark edited pull request #28: Add experimental JavaScript package - https://github.com/YoWASP/yosys/pull/28
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<_whitenotifier-3> [amaranth-soc] koblonczek opened issue #60: Signature.create in amaranth-soc interfaces is incompatible with Signature.create from latest Amaranth - https://github.com/amaranth-lang/amaranth-soc/issues/60
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<iposthuman[m]> After a good night sleep i found my PLL error. Can you spot it?```python... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/OwudmOWLnkgKLZpRywyVjZWv>)
<iposthuman[m]> It was right in front of my face 🤭
<whitequark[cis]> I do not
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<jfng[m]> the SoC meeting today is cancelled, as it is overlapping with another meeting; sorry for the short notice
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<vegard_e[m]> the constants that are decimal literals and not binary?
<iposthuman[m]> I was missing the "0b" prefix. vegard_e (@_discord_157944445168254976:catircservices.org) That is correct. 😅
<galibert[m]> Amaranth was not annoyed that 101 does not fit at all into 3 bits?
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<iposthuman[m]> Apparently not. I would synthesize just fine.
<iposthuman[m]> s/I/iI/
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<galibert[m]> Catherine: That could use a warning, no?
<whitequark[cis]> galibert: hmm, yeah
<galibert[m]> Trying to think of a case where it would be annoying, but I don't see one
<galibert[m]> Maybe not warning on a negative value on an unsigned const if the value fits ?
<galibert[m]> So that people canb use -1 for all bits 1
<galibert[m]> s/canb/can/
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