<ravenslofty[m]>
unfortunately Amaranth does not support uninitialised memories
<ravenslofty[m]>
or....perhaps "considers them a misfeature" is a better phrase
<ldcd[m]>
Yeah that was my understanding
<whitequark[cis]>
this support will be added because SRAMs in ASICs are not representable otherwise
<whitequark[cis]>
it will require a considerable amount of work because the simulator must now support
<whitequark[cis]>
* now support 'x
<ldcd[m]>
Oh also
<ldcd[m]>
when I create a memory with a readport and a write port do I add both ports and the memory as submodules, or just the ports
<ldcd[m]>
SyncFIFO does the second and SyncFIFOBuffered does the first
<whitequark[cis]>
we're actually in the middle of a transition from adding ports as submodules to adding the memory as a submodule for various historical reasons
<whitequark[cis]>
it will be just the memory eventually, right now both work
<ldcd[m]>
Ah ok
<ldcd[m]>
was getting weird results with the first
<ldcd[m]>
Ok adding just the module gives something more like what I would expect, lets see if vivado likes it better
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<zyp[m]>
in the async simulator interface I'm prototyping, I'm using get/set to read and write values; what are good pairs to interact with streams? I'd use get/put and get_packet/put_packet if not for the fact that get overlaps
<zyp[m]>
send/recv for single transfers sounds kinda wrong
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<zyp[m]>
<zyp[m]> "I rewrote the simulation I did..." <- > <@vegard_e:matrix.org> I rewrote the simulation I did yesterday using the async API I did a couple of weeks ago: https://paste.jvnv.net/view/NUcbq
<zyp[m]>
> gonna try this out a bit as I add streams and see how the ergonomics works out
<ravenslofty[m]>
don't you want to blink some lights on a board, or react to switches?
<galibert[m]>
ravenslofty: the tradition with amaranth on fpga is not to having anything on top but to instantiate gpio modules, e.g. have everything explicit
<MuddassirAli[m]>
ravenslofty[m]: so what should I do?🥲
<galibert[m]>
Do you actually have a fpga devboard or are you doing everything in simulation?
<MuddassirAli[m]>
galibert[m]: on a simulation only but i want to run this on fpga later
<galibert[m]>
in simulation you don't really need ports. Note that you don't really need verilog either, amaranth internal simulation facilities are nice
<MuddassirAli[m]>
let me clear i have the design, i want to run this on arty A7 fpga so i need verilog file but it can not generate a single file
<MuddassirAli[m]>
it generate verilog files for each and every module but not for top module
<ravenslofty[m]>
Uh, I'm pretty sure it should: there should be a "top" module
<iposthuman[m]>
I finally got SRAM to work. Thanks @Catherine for the review and suggestions, and @galibert for your pointers, among many others--much appreciated. Two things caused it to fail (actually many but...), improper signaling and WE not being held long enough. The video shows the memory addresses (vertical pmod) and the status code (horizontal pmod) 🙂