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[amaranth-lang/amaranth-stdio] whitequark d3e141d - CI: bump Python version to 3.8.
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<cr1901>
I don't actually know which channel to put this on, but I skimmed the rust-embedded chat about the CSR bus. Reads/writes will be "cached" to prevent torn reads/writes. Last bus-width write to cache writes the reg, First bus-width read reads from reg to cache. Is that correct?