whitequark changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings on Mondays at 1700 UTC · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang
phire has quit [Quit: No Ping reply in 180 seconds.]
phire has joined #amaranth-lang
DX-MON has quit [Server closed connection]
DX-MON has joined #amaranth-lang
Degi_ has joined #amaranth-lang
Degi has quit [Ping timeout: 260 seconds]
Degi_ is now known as Degi
eigenform has quit [Server closed connection]
eigenform has joined #amaranth-lang
<_whitenotifier-6> [amaranth-lang/amaranth-soc] whitequark pushed 1 commit to main [+0/-0/±1] https://github.com/amaranth-lang/amaranth-soc/compare/d2185e3082c8...d2ca157d755a
<_whitenotifier-6> [amaranth-lang/amaranth-soc] whitequark d2ca157 - CI: bump Python version to 3.8.
<_whitenotifier-6> [amaranth-lang/amaranth-stdio] whitequark pushed 1 commit to main [+0/-0/±1] https://github.com/amaranth-lang/amaranth-stdio/compare/f41e7e50ef1e...d3e141d8c71c
<_whitenotifier-6> [amaranth-lang/amaranth-stdio] whitequark d3e141d - CI: bump Python version to 3.8.
allysonprolisko[ has joined #amaranth-lang
jjsuperpower has quit [Ping timeout: 250 seconds]
esden has quit [Server closed connection]
esden has joined #amaranth-lang
sorear_ is now known as sorear
<cr1901> I don't actually know which channel to put this on, but I skimmed the rust-embedded chat about the CSR bus. Reads/writes will be "cached" to prevent torn reads/writes. Last bus-width write to cache writes the reg, First bus-width read reads from reg to cache. Is that correct?