whitequark changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings on Mondays at 1700 UTC · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang
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<FL4SHK> good news, my interfaces and arrays of interfaces implementation is now complete
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<whitequark> <galibert[m]> "Ah damn, I'm doing things (..." <- this is an amaranth bug
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<d1b2> <Olivier Galibert> Ah ok, I thought it was a python extensibility limitation
<whitequark> My health has suffered due to the heat wave so today's meeting is cancelled
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<galibert[m]> Take care of yourself
<galibert[m]> Is there an auto-numbering method that fits well with amaranth.lib.enum.Enum?
<whitequark> the default Python one should work
<galibert[m]> ok. Annoyingly the default pytohn ones start at 1, which is sub-optimal for amaranth
<galibert[m]> If .bool() different than .any() ?
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<mwk> galibert[m]: they're equivalent, though they produce a different op on RTLIL level (and possibly in output Verilog)
<mwk> ... oh, Verilog backend actually treats them equivalently
<mwk> so yeah, no real difference
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<galibert[m]> ok cool, I'm not missing anythng then
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<FL4SHK> the interfaces feature I came up with is usable with `Instance`s
<FL4SHK> if you want some ideas for how to do this kind of thing
<FL4SHK> then I'd be willing to offer input
<FL4SHK> though I think my `Splitintf` is less general than Amaranth's interface objects in one way: there's no fan-out
<FL4SHK> well
<FL4SHK> I think you can only have one of my `Splitintf`s connected to one other `Splitintf`
<FL4SHK> I'm not completely sure if it works
<FL4SHK> I might be wrong
<FL4SHK> I got arrays of `Splitintf` to work too though
<FL4SHK> two `Splitintf` members of a parent `Splitintf` can still be connected separately
<FL4SHK> that and every element of a `Splitintfarr` can be connected separately
<FL4SHK> I set up a "tag" system
<FL4SHK> So that only `Splitintf`s with the same `tag` field would be connected
<FL4SHK> it seems to work pretty well, and is pretty orthogonal
<FL4SHK> I converted some of my existing code to use my `Splitintf`
<FL4SHK> and then I ran my formal verification again
<FL4SHK> that passed
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<d1b2> <Olivier Galibert> Is there a good resource to learn everything useful about CDC on fpgas (or possibly in general)?
<cr1901> Olivier Galibert: https://www.eetimes.com/understanding-clock-domain-crossing-issues/ This is, AFAIK, the most-cited article on all of EETimes. For good reason.
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