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<d1b2>
<dave berkeley> I have a pair of Stream-like interfaces (valid, ready, payload(s) ) which I want to use to connect between modules on 2 different clock domains. I'm not sure where to start. The ClockDomainCrossing module in Litex seems to be what I want. Not sure how to test them either. Are there any examples I should look at?
<miek>
AsyncFIFO is probably what you want
<d1b2>
<dave berkeley> Just looking at the amlib and Luna code.
<d1b2>
<dave berkeley> Thanks. Just looking at how it is used. Not sure how to simulate modules with different clock domains.
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<adamgreig[m]>
if you're using pysim, you can call simulator.add_clock multiple times for each domain and then add different testbench processes to each domain
<adamgreig[m]>
like `simulator.add_clock(1/10e6, domain="sync"); simulator.add_clock(1/1e6, domain="slow"); simulator.add_sync_process(tb1, domain="sync"); simulator.add_sync_process(tb2, domain="slow")`
<d1b2>
<dave berkeley> just realised the Tick(domain) syntax. That makes sense.
<adamgreig[m]>
if you've added the sync process with a specific domain anyway you can just use yield in the testbench to advance one cycle
<d1b2>
<dave berkeley> Thanks.
<Degi>
Did anybody make a DDR(3) memory interface in Amaranth yet?
<koschei[m]>
I’d love to have one. Maybe the ULX4M folks have something?