<d1b2>
<MCE> excuse a dumb question, but does Amaranth have any equivalent of $display?
<adamgreig[m]>
usually if you're using pysim to simulate some amaranth design you can just use python's normal print() as required (or other outputs, or asserts, or integrate with pytest, etc)
<jevinskie[m]>
MCE: it’s gated on yosys support iirc
<d1b2>
<MCE> So in this type of simulation, the design is not elaborated once at the start?
<jevinskie[m]>
It is but the elaboration to verilog has to go through yosys IIRC
<d1b2>
<bob_twinkles> it's a question of how you're simulating the design
<d1b2>
<bob_twinkles> if you're exporting to a verilog testbench, then you probably need 2459
<d1b2>
<bob_twinkles> if you're using Amaranth's built-in "pysim" infrastructure, you can use thing like yield sig to get signal values and just use normal python prints (or python asserts, or any other python code)
<d1b2>
<bob_twinkles> if you're exporting just your design to verilog/cxxrtl and simulating with a custom testbench outside of Amaranth, then you can do your normal thing/use the full power of C++
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