11:13 <peterm6881> Lichee Zero managed to expose pretty much everything on a 44 mm by 25 mm board

11:17 <peterm6881> 60 1.27 mm pitch pins and 34 2.54 mm pitch pins. 94 pins

11:21 <peterm6881> i2c0, i2c1, UART0, UART1, UART2, SPI, SDC0, SDC1, audio line out, microphone in, Ethernet, and USB, plus 5 GPIO pins

11:24 <peterm6881> It's a piece of work. And Buildroot evidently recognised that

11:25 <peterm6881> it'll be good to take over production of this

11:29 <peterm6881> also, morning Xogium

11:46 <peterm6881> I thought the dock board was an add-on, like some kind of carrier board. But it isnt, its a board with the layout of the Lichee Nano integrated into it

11:46 <peterm6881> Zero

11:48 <peterm6881> the different dts is explained by the fact the dock board has a camera header, hence the RGB stuff

11:49 <peterm6881> its useful that although people often misname it as LicheePi Zero or Lichee Pi Zero, its proper name is Lichee Zero

11:50 <peterm6881> although unhelpfully, back in the day they set up https://licheepizero.us/

11:50 <Speedsaver> Title: Home | Lichee Pi Zero (at licheepizero.us)

11:51 <peterm6881> but the board itself is silk screen printed Lichee Zero and SUNXI

11:52 <peterm6881> we're on the right track Xogium

11:52 <peterm6881> we wont be referring to it as a Pi

12:48 <peterm6881> the V3s has 2 channel audio output

12:48 <peterm6881> front left, front right

12:49 <peterm6881> you could have binaural playback

12:50 <Xogium> sure. Just a pair of headphones in the headphone jack, and off you go, binaural

12:58 <peterm6881> the F1C200's was mono

15:49 <peterm6881> The processor has optimized external memory interfaces to SPI NAND/ Nor flash, SD/MMC and SDRAM port. SDRAM port

15:49 <peterm6881> can be configured to support DDR2, DDR3, DDR3L, LPDDR2 or LPDDR

15:50 <peterm6881> 2.1.2.2. SDRAM

15:50 <peterm6881>  Support clock frequency up to 667MHz(DDR3-1333)

15:50 <peterm6881>  Support 2 chip selects

15:50 <peterm6881>  Up to 2GB address space

15:50 <peterm6881>  Compatible with JEDEC standard DDR2 /DDR3 /DDR3L/LPDDR2/LPDDR3 SDRAM

15:50 <peterm6881>  16/8-bit bus width

15:50 <peterm6881>  16 address signal lines and 3 bank signal lines

15:50 <peterm6881>  Support Dual rank

15:51 <peterm6881>  Support Memory Dynamic Frequency Scale(MDFS)

15:52 <peterm6881> we could kick some ass with that

15:52 <peterm6881> 2 GB DDR3 1333 MHz

15:53 <peterm6881> but hey, just sayin'