whitequark[cis] changed the topic of #glasgow to: https://glasgow-embedded.org · digital interface explorer · https://www.crowdsupply.com/1bitsquared/glasgow · code https://github.com/GlasgowEmbedded/glasgow · logs https://libera.irclog.whitequark.org/glasgow · matrix #glasgow-interface-explorer:matrix.org · discord https://1bitsquared.com/pages/chat
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<sigstoat[m]> can the glasgow software retain/show me the verilog generated from my applet during the synthesis process? or do i need to invoke amaranth myself to get that?
<whitequark[cis]> glasgow build --rev C3 -t v applet
<whitequark[cis]> it doesn't actually use verilog at any point in the build process when you use glasgow run
<whitequark[cis]> (it goes directly from Amaranth to a netlist in Yosys IR format)
<whitequark[cis]> so you have to build Verilog separately if you want that
<sigstoat[m]> ahh.
<sigstoat[m]> hmm. the -t option in my copy of 0.1.dev2044+g21f9ed4.d20240508 says it only knows about 'zip', 'archive', 'il', 'rtlil', 'bin', 'bitstream'
<whitequark[cis]> oh. right.
<whitequark[cis]> well, generate IL and then convert it to Verilog manually using yowasp-yosys applet.il -o applet.v
<sigstoat[m]> excellent. thank you.
<whitequark[cis]> are your skills primarily in Verilog?
<sigstoat[m]> to the extent that i have any, yes.
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<whitequark[cis]> makes sense!
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<chipb> whitequark[cis]: re: "they did surgery on a microprocessor" -- while I can't say how common it is, that's not unheard of in industry https://en.wikipedia.org/wiki/Focused_ion_beam
<whitequark[cis]> in this case it's the biology that's interesting
<chipb> samples come back with a fatal bug in a block? maybe you can kneecap it in X% of the units so you can proceed with testing while the next stepping is prepared.
<whitequark[cis]> here's an amaranth logo on a piece of uhhh i think tin
<chipb> oh, neat.
<whitequark[cis]> it was put there using amaranth and glasgow!
<whitequark[cis]> so, very contextually relevant
<chipb> sorry, I wasn't sure if you had run across the technique before.
<whitequark[cis]> oh i'm just bragging :3
<whitequark[cis]> i don't mind
<Darius> pew pew
<Darius> whitequark[cis]: surely you want to turn it into GCode 8-)
<SnoopJ> oh neat I hadn't seen the logo image, just the images from the thermal sensor pew-pew I think
<sigstoat[m]> hooray, my second applet works. i can now toggle a pin with configurable frequency and duty cycle.
<whitequark[cis]> sweet
<whitequark[cis]> yeah we should probably have that as standard
<whitequark[cis]> like glasgow run control-pwm or something
<whitequark[cis]> and have the ability to do cycle-accurate and simultaneous switching of multiple PWM outputs
<sigstoat[m]> i was cribbing heavily from the servo code. which motivated a question. it sends a 2 byte value across, and uses two states in the FSM for the task. i was sending some 4 byte values (i wanted low frequencies), so i just extended that to 4 states. works fine of course, but is there something more clever to do?
<whitequark[cis]> naw that's all right
<whitequark[cis]> the FSMs can get pretty unwieldy but it's what we do
<whitequark[cis]> eventually I'll probably add some sort of protobuf-like system but it's hard to design a nice one
<whitequark[cis]> you could, if you want, do a for index in range(4): and then interpolate state names and so on
<whitequark[cis]> but it's kind of its own brand of verbose
<sigstoat[m]> oh i see how that'd work. yeah. i'll save that for when i've got to send a >8 byte value or something.
<whitequark[cis]> you can also use an explicit index variable. there's a few ways and it mostly just doesn't matter what you do
<whitequark[cis]> now that amaranth has real data structures (lib.data) we can say "ok, i want to receive one of these / n of these / union of these"
<whitequark[cis]> but it wasn't really a thing at the time
<sigstoat[m]> if you're taking suggestions on standard applets, my first one was for just flipping a single pin. sscaling that up beyond the toy level, omething that gave a RPi.GPIO-esque interface at the repl/script level might be handy.
<whitequark[cis]> oh i have my hands more than full with amaranth development and maintenance
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<mr_haxwell[m]> There is a lab full of FIB machines in my building and whenever I get to tour it I swear they use black magic.
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<nekrondev[m]> hi Cath... many thanks for building and maintaining glasgow... I've got a question regarding https://github.com/GlasgowEmbedded/glasgow/issues/552 .. how practically does this affect using the current device revision (C3)? I'm new into this and can't reason about it if it's only an issue when there is some edge case hacking where you need to power the DUT or does it interfere using glasgow on some common setup?
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<theorbtwo[m]> What is the point of the trailing "_t" on pad names? I see where it comes from -- https://github.com/GlasgowEmbedded/glasgow/blob/8440e6176bffbb14363c0d39f0e291faab5495cb/software/glasgow/gateware/pads.py#L38 -- but why?
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<theorbtwo[m]> IT WORKS!
<theorbtwo[m]> https://github.com/theorbtwo/glasgow/tree/uart-extra-pins if anybody wants to see.
<Wonka> btw, frame.work won. The notebook, announced for delivery on May 11th, already arrived. ;)
<castaway[m]> woot
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<cyborg_ar> wheeeeee
<cyborg_ar> just got my glasgow
<cyborg_ar> is there an accurate STEP model of the C3 board available?
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<_whitenotifier-f> [glasgow] nekrondev commented on issue #552: Reloading FPGA bitstream causes all outputs whose Vio is enabled to strongly drive high - https://github.com/GlasgowEmbedded/glasgow/issues/552#issuecomment-2101126357
<cyborg_ar> managed to export one from the kicad project
<cyborg_ar> one footprint was missing
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