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02:31
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tpw_rules >
whitequark[cis]: how might that cursedness with abc and macos manifest? i'm noticing that the analyzer test fails on on recent yosys but the glasgow version i'm using is kind of old
02:34
<
tpw_rules >
specifically it fails because the timing analysis is 29.84MHz instead of 30
02:41
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whitequark[cis] >
that's just normal fpga stuff
02:42
<
tpw_rules >
should that be a test error?
02:46
<
tpw_rules >
(not entirely clear where it is being converted into an error, i'll have to poke harder)
02:48
<
tpw_rules >
ah, nextpnr does it
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04:21
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esden[m] >
Some good progress! 🙂
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Darius >
esden: nice in-tray for your through hole solderer come Monday :D
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06:15
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esden[m] >
Yep, so many boards. 🙂 Some more top sides to do tomorrow for this round. Then I have to go back to back side assembly again.
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prop_head_mania[ >
WOWEEE!!!
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20:57
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esden[m] >
Ok finished this batch today. All ready for the through hole parts. This should bring us over the 50% mark 🙂
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whitequark[cis] >
awawa
20:59
<
whitequark[cis] >
that is so many ✨
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josHua[m] >
wowow I am excited
21:34
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esden[m] >
two more batches like this and we should be done fulfilling the campaign and pre-orders
21:34
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galibert[m] >
Niiiice
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