whitequark changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings on Mondays at 1700 UTC · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang
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<_whitenotifier-9> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/a124f4b74fcf...c74755022105
<_whitenotifier-9> [YoWASP/yosys] whitequark c747550 - Update dependencies.
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<_whitenotifier-9> [amaranth] jeremyherbert opened issue #745: WARNING: Generating metadata for package amaranth produced metadata for project name unknown. Fix your #egg=amaranth fragments. - https://github.com/amaranth-lang/amaranth/issues/745
<_whitenotifier-9> [amaranth] whitequark commented on issue #745: WARNING: Generating metadata for package amaranth produced metadata for project name unknown. Fix your #egg=amaranth fragments. - https://github.com/amaranth-lang/amaranth/issues/745#issuecomment-1425786649
<_whitenotifier-9> [amaranth] miek commented on issue #745: WARNING: Generating metadata for package amaranth produced metadata for project name unknown. Fix your #egg=amaranth fragments. - https://github.com/amaranth-lang/amaranth/issues/745#issuecomment-1425804229
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<_whitenotifier-9> [amaranth] whitequark commented on issue #745: WARNING: Generating metadata for package amaranth produced metadata for project name unknown. Fix your #egg=amaranth fragments. - https://github.com/amaranth-lang/amaranth/issues/745#issuecomment-1425827851
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<_whitenotifier-9> [amaranth] ydnatag opened issue #746: Building verilog output with synplify pro - https://github.com/amaranth-lang/amaranth/issues/746
<_whitenotifier-9> [amaranth] whitequark commented on issue #746: Building verilog output with synplify pro - https://github.com/amaranth-lang/amaranth/issues/746#issuecomment-1426168418
<_whitenotifier-9> [amaranth] ydnatag commented on issue #746: Building verilog output with synplify pro - https://github.com/amaranth-lang/amaranth/issues/746#issuecomment-1426180245
<_whitenotifier-9> [amaranth] whitequark commented on issue #746: Building verilog output with synplify pro - https://github.com/amaranth-lang/amaranth/issues/746#issuecomment-1426186494
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