00:21 <_whitenotifier-7> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/nextpnr/compare/8df4b0413591...43a05e17765d

00:21 <_whitenotifier-7> [YoWASP/nextpnr] whitequark 43a05e1 - Update dependencies.

00:52 <d1b2> <TheManiacalLemon> Anyone know if there's a way to embed some Verilog literals inside generated code when running the Verilog backend?

00:53 <d1b2> <TheManiacalLemon> i.e. if I want to run the generated verilog inside iverilog, I need the initial begin with the $dumpvars inside the top module. Otherwise, I think the only workaround would be to wrap the generated Amaranth file in another Verilog file with $dumpvars already inside it

00:55 <_whitenotifier-7> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/fc38c3b440f1...114c296035a4

00:55 <_whitenotifier-7> [YoWASP/yosys] whitequark 114c296 - Update dependencies.

01:08 <d1b2> <TheManiacalLemon> update: it does appear that wrapping the file is relatively painless as long as I passthrough all the top level signals