azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<hammdist>
#LOCATE COMP "flash_clk" SITE "U3"; <-- why is this commented out in examples/ulx3s/ulx3s_v20.lpf in prjtrellis. has anyone got the flash connection to work?
<hammdist>
I'm trying to connect to the configuration flash but I can't place the clock signal on U3; the tool claims there is no such pin
<hammdist>
the pins is defined in ECP5UM5G-45Pinout.csv -- 153,CCLK,8,MCLK/SCK,-,-,-,AE3,U3,U16
<hammdist>
so there is no U3 for CABGA381 in ECP5/LFE5UM5G-45F/iodb.json
<hammdist>
prjtrellis/tools/read_pinout.py I think the problem is that this script skips the pin as it doesn't begin with P (and there is no clear way to implement get_bel in this case)
<hammdist>
hm. the datasheet usually says "when not in configuration, it can be used as a general purpose I/O pin"
<hammdist>
it does say this for the other flash pins, but not for CCLK
<hammdist>
maybe there is no way to access the flash from the fpga after all
<hammdist>
ah there is this USRMCLK primitive
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<tnt>
hammdist: yeah, seems you found the answer, but that pin is not a normal IO pin basically.
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<hammdist>
well using USRMCLK I was able to read the first 3 bytes of the ID information of the flash chip. seems to work
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