azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
Forty-Bot has joined ##openfpga
<Forty-Bot> is this correct timing for external clock to data read/write delays: https://docs.google.com/spreadsheets/d/1MLHXq01gRvLviAHvv-He8i3iddVRyaeM2xKb9xDmTGg ?
<Forty-Bot> numbers are pulled from icestorm, but what I'm interested in is whether I'm missing a path
Degi has quit [Ping timeout: 240 seconds]
Degi has joined ##openfpga
GenTooMan has quit [Ping timeout: 244 seconds]
GenTooMan has joined ##openfpga
kristianpaul has joined ##openfpga
kristianpaul has quit [Read error: Connection reset by peer]
kristianpaul has joined ##openfpga
specing_ has joined ##openfpga
specing has quit [Killed (NickServ (GHOST command used by specing_))]
specing_ is now known as specing
GenTooMan has quit [Ping timeout: 244 seconds]
GenTooMan has joined ##openfpga
specing has quit [Quit: ZNC - https://znc.in]
lkcl- has quit [Read error: Connection reset by peer]
specing has joined ##openfpga
lkcl has joined ##openfpga