azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<Forty-Bot>
does nextpnr support sampling signals synchronous to an external clock?
<Forty-Bot>
it doesn't seem like there are constraints for e.g. setup and hold
<Forty-Bot>
can I get away with just routing a clock directly to a global buffer and using IO cells?
<Forty-Bot>
or do I have to oversample?
<tnt>
There is no IO constraints no.
<tnt>
What you can do is _highly_ dependent on your application, frequency, target FPGA and even which pins you decided to connect your signals to ... so no universal answer here.
<Forty-Bot>
are there any pnr tools which suppport this?
<Forty-Bot>
looks like vtr supports it; but ice40 support seems lacking