azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<tplaten> When I try to route a design that uses ddr3, I get Warning: Failed to find a route for arc 2 of net ddrphy_ddr3_0__a__o_fclk.
<tplaten> ddrphy_ddr3_0__a__o_fclk is defined as a clock signal in nmigen ClockSignal("dramsync2x"), the other one is ClockSignal("dramsync"). I'guess that there must be a PLL between those two clock signals
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