azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
peepsalot has quit [Read error: Connection reset by peer]
peepsalot has joined ##openfpga
specing_ has joined ##openfpga
specing has quit [Killed (NickServ (GHOST command used by specing_))]
specing_ is now known as specing
Degi has quit [Ping timeout: 260 seconds]
Degi has joined ##openfpga
emeb_mac has quit [Quit: Leaving.]
kristianpaul has quit [Remote host closed the connection]
kristianpaul has joined ##openfpga
balrog has quit [Quit: Bye]
specing has quit [Killed (NickServ (GHOST command used by specing_))]
specing_ has joined ##openfpga
balrog has joined ##openfpga
specing_ is now known as specing
emeb_mac has joined ##openfpga
emeb has joined ##openfpga
tplaten has joined ##openfpga
<tplaten>
When I try to build ls2 (https://git.libre-soc.org/?p=ls2.git) for the orangecrab, I get an error message that seams to be unclear to me, I was unable to fix that error
<tplaten>
DQS group mismatch, port DQSW270 of 'ddrphy.U$$46' in group LDQ41 is driven by DQSBUFM 'ddrphy.U$$45' in group LDQ53
<tplaten>
I assumed that I swapped LDQS with UDQS, and after *fixing* that I get
<tplaten>
ERROR: DQS group mismatch, port DQSW270 of 'ddrphy.U$$88' in group LDQ53 is driven by DQSBUFM 'ddrphy.U$$45' in group LDQ41
<tplaten>
If I understand everything correctly there are two ddr3 phys on the fpga, one on bank 6 and one on bank 7
emeb has quit [Remote host closed the connection]
emeb has joined ##openfpga
cr1901_ has joined ##openfpga
cr1901 has quit [Ping timeout: 272 seconds]
tplaten has left ##openfpga [##openfpga]
<gatecat>
in case tplaten is checking the logs, the DQS stuff is split into groups smaller than banks, called DQS groups if you check the pinout file, and all DQS+data for a given DQSBUFM must be contained within the same group
cr1901 has joined ##openfpga
cr1901_ has quit [Ping timeout: 260 seconds]
specing has quit [Ping timeout: 240 seconds]
specing has joined ##openfpga
emeb has quit [Quit: Leaving.]
<azonenberg>
gatecat: so similar PHY structure to 7 series in that regard?