whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<vup[m]> Catherine: in `cxxrtl`, two back to back `.step()` should not change the value of output ports, right?
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<whitequark[cis]> not unless there is a bug somewhere
<whitequark[cis]> are you using submodules or black boxes?
<vup[m]> nope
<whitequark[cis]> any feedback arcs?
<whitequark[cis]> do you get convergence on the first delta?
<vup[m]> (assuming with submodules you mean -noflatten)
<whitequark[cis]> yes
<vup[m]> no feedback arcs, but I do a splitnets -driver; clean -purge because I get them otherwise
<whitequark[cis]> does it work if you skip splitnets?
<vup[m]> whitequark[cis]: with splitnets yes
<vup[m]> whitequark[cis]: yes
<whitequark[cis]> right
<whitequark[cis]> is the netlist weird somehow or is it just normal?
<whitequark[cis]> i realize this is a very subjective thing
<whitequark[cis]> oh, any clocks generated by logic?
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<vup[m]> no, no clocks generated by logic
<vup[m]> but I think you could say its a weird netlist. Its (partly) vhdl synthed by ghdl with a "weird" codestyle.
<vup[m]> take this for example: https://paste.niemo.de/raw/mopehuhoru
<vup[m]> ghdl makes internal_bus a single very wide signal, which is the source of all the feedback arcs...
<vup[m]> s/mopehuhoru/seweseteyi/
<vup[m]> vup[m]: (updated the link to have a more self-contained example)
<whitequark[cis]> that doesn't seem unreasonable
<whitequark[cis]> if you have an MCVE as an RTLIL netlist feel free to submit an issue at least
<whitequark[cis]> RTLIL + C++ driver
<vup[m]> will do
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