whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<mewt> is there any reasonable way to view a schematic for your yosys output, similar to what Vivado produces?
<mewt> guessing not, but curious
<mewt> show runs for...a very long time, something like 9 hours now
<jix> show is the only thing we have, for anything that's not tiny you need to use the selection argument to select a smaller part of the design for it to be useful though
<jix> the limitation here is what graphviz (which show uses) can layout in practice
<mewt> right
<jix> there's also https://github.com/nturley/netlistsvg which uses the eclipse layout kernel instead of graphviz, that seems to produce a more schematic like layout than graphviz, but I have never used it and have no idea if it scales better or worse
<mewt> thanks for the answer, I guess I can either select or just look at another way to troubleshoot my design
<jix> somewhat cursed alternative: export the design as structural verilog (write_verilog -noexpr) and load it into vivado (no idea if that would actually give you a usable schematic view)
<mewt> Yeah, I think there's gotta be a better way to do what I'm doing. This was just a potential debugging method
<jix> often I end up using running `show foo/bar %ci2; show foo/bar %ci4; show foo/bar %ci6; ...` to see the input cone of a signal bar in module foo with an increasing depth limit
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<FL4SHK> hey... thanks for the great tooling!
<FL4SHK> It is helping me prove my design
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