06:43 <Myrl-saki> Hi. :) I finally got an ECP5 board, how do I use registered output BRAM?

06:45 <Myrl-saki> Oh wait.

06:45 <Myrl-saki> In hindsight, maybe it's getting inferred? And that's why I'm having weird timings.

06:46 <Myrl-saki> TL;DR is that the slowest path right now is the BRAM, so I wanted to use registered output. So I did. But it still considers the output to not be regisetred.

06:46 <Myrl-saki> At least if I'm understanding it correctly..

06:47 <Myrl-saki> https://gist.github.com/adrianparvino/ce9d10bd0be389e9bffdd0626fe83990

06:48 <tnt> you can check in the .json to see if that ram is configured with output register.

06:49 <Myrl-saki> Huh true

06:49 <Myrl-saki> Ah

06:49 <Myrl-saki> test

06:49 <Myrl-saki> "REGMODE_A": "NOREG",

06:50 <Myrl-saki> Seems like that's a no.

06:50 <tnt> I'm not even sure if ecp5 infer ram supports output reg TBH.

06:51 <Myrl-saki> Okay, so that's answered, at least.

06:51 <Myrl-saki> Hm.

06:51 <Myrl-saki> Yeah, maybe I'm misunderstanding somethign here?

06:51 <Myrl-saki> ```

06:52 <Myrl-saki> Info: 5.6 5.6 Source ram.cells_a.0.1.DOA7

06:52 <Myrl-saki> Is this the input or an output of the RAM?

06:52 <Myrl-saki> Whoops, I better send my RAM implementation too.

06:52 <tnt> output.

06:52 <tnt> It's the time from the clock edge to the moment the data shows up on the data out pins.

06:52 <Myrl-saki> https://gist.github.com/adrianparvino/238392f626a15f70e44286527f51a75b

06:53 <tnt> The ECP5 BRAM have a very long clock-to-out on BRAMs.

06:53 <tnt> well this ram model doesn't have an output register ...

06:54 <Myrl-saki> Wait, give me a bit to think about this lol. So, my original implementation was to just do `assign out[...] = cells[addr];`

06:54 <tnt> enabling out_reg on ecp5 means you have the input registers (because they are bram, always synchronous), then another register on the data output. So you have a read latency of 2 cycles.

06:55 <tnt> Your implementation was an asynchronous read ram ... that doesn't even _map_ to BRAMs at all ...

06:56 <Myrl-saki> Okay, I think I get it. So the way this works is that it actually latches the address?

06:57 <Myrl-saki> Like, one way I can see this is: `assign out[...] = cells[a_reg]; ... a_reg <= addr;`?

07:05 <tnt> yes

07:50 <Myrl-saki> Can block RAM be considered as async write?

07:51 <Myrl-saki> Wait, that kind of makes no sense does it

08:00 <lofty> Myrl-saki: you basically never want async write

08:01 <Myrl-saki> Yeah, I kind of had a messup in understanding "async" and "sync" there, but I think I get it now.

13:40 <Myrl-saki> Okay, stupid question, but like

13:40 <Myrl-saki> Am I having a hard time timing, because I'm using BRAM and IO at the same time? And using combinatorial logic between them

13:42 <Myrl-saki> A bit more specific: I'm progressively converting my CPU and peripherals into Wishbone, and it's not going as fast as I expected. This wasn't a problem on the Tang Nano 9K, so I'm surprised that it's a problem on this board.

13:45 <Myrl-saki> Hm, I think the coordinates should reveal if that's the problem, but I don't think it's that.

15:14 <gatecat> somlo: I think https://github.com/YosysHQ/nextpnr/pull/1249, but I haven't actually tested with Python 3.13

15:34 <somlo> gatecat: thanks, I'll run some tests and report back