whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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* povik wrote a toy technology mapper
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<lofty> povik: welcome to the club
<povik> thanks :)
<povik> when do we meet?
<lofty> Whenever someone gets annoyed at an ABC bug /j
<lofty> povik: looking through your code, I do notice a few things worth mentioning
<povik> shoot away
<lofty> povik: DepthEval2 is, uh, more of an ABC quirk than an implementation requirement; you don't need it
<povik> i copied the passes i saw in the paper i reference
<povik> though it's not surprising that's what abc does of course
<lofty> Yes, I've written two priority cut based mappers
<povik> ok, go ahead
<lofty> My understanding of Mishchenko's email about this is that ABC runs two separate mapping passes, one with DepthEval and the other with DepthEval2
<lofty> Actually, I might as well put the email into a gist
<lofty> There have also been enhancements and generalisations of the priority cut algorithm, if you're curious
<povik> a bit
<povik> especially if it's something simple i can quickly throw in and see an improvement in the benchmark :p
<povik> it's a toy after all...
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<povik> i got that part about the stitching from the paper but when i saw some benefit from running DepthEval followed by DepthEval2 so i left it in
<povik> s/so i left/i left/
<lofty> povik: there's a paper called WireMap; it's basically just the priority cut mapper but with a few more heuristics
<povik> got it!
<lofty> povik: another thing, you are technically meant to alternate area flow and exact area, rather than running AF twice and then EA
<povik> btw if you can suggest off the top of head a better command for preprocessing of the aig than `abc -g aig` then don't hesitate to share
<povik> ah
<lofty> povik: I think that's a fine command to use; there's `aigmap` for a direct mapping of Yosys cells to AIG
<lofty> But that means you don't have any optimisations
<povik> yeah, i was thinking of optimisations
<povik> the other way i added $lt and friends to aigmap... :)
<lofty> I will however point out that separate optimization and mapping will never be quite as good as ABC
<povik> let me guess... structural choices?
<lofty> Correct
<lofty> I did sketch out with some people how that could be implemented, but whether it'll ever actually get done is an eternal question
<lofty> (your source code also threw me a little bit when I read it; what you call lag is what the literature calls slack, and it took a moment to realise what you meant)
<povik> hah, we should do s/lag/slack/ then
<povik> but i think i saw someone call it lag in a paper
<povik> or something similar anyway...
<lofty> Actually, let me double check your source :p
<povik> see yosys_export(), lag means you should throw the given amount of $ff on the path
<povik> ah it iterates over initvals (initvals.size() == lag) so that's not exactly clear
<lofty> If you were daring enough you could operate directly with RTLIL and skip the import/output stages
<povik> i would see the elegance in that but i expect it to be slow
<povik> too slow for a toy even
<povik> also i like to reference the fanins without going through a dict
<povik> there's no dicts in there other than the import/export stages!
<povik> and i'm happy about that :p
<lofty> povik: I think the actual literature term might be arrival rather than slack. It's the maximum number of LUTs you have to go through to reach this LUT from the PIs
<povik> that's not what i mean with lag though
<povik> it's the register delay from one node to another, going through the given edge
<povik> and it's adjusted during retiming
<lofty> Uh.
<povik> or would be, at least...
<lofty> Right, so it's sequential. That's why it was confusing.
<povik> yeah, i wanted to play with retiming first, that's why the lag is implemented in the first place
<povik> then i got distracted with wanting to see how much effort it takes to get close to abc on combinatorial mapping only
<lofty> I do think my implementation is more elegant than yours, but that's just because C++ is a bit clumsy in general
<povik> :D
<povik> thanks.
<povik> /j
<lofty> (Using majority-inverter graphs was a mistake)
<povik> what's majority-inverter?
<lofty> Three input majority function: (A & B) | (A & C) | (B & C)
<povik> ah
<lofty> With invertible inputs
<lofty> Don't look at it, it's a Synopsys patent minefield
<lofty> But I only found that out after the fact
<lofty> But the priority cut algorithm is surprisingly simple when you have sufficient expressive power to say what without saying how
<povik> i suppose there's a paper somewhere that discusses the benefits of majority-inverters
<povik> is that something they use extensively in the proprietary compiler?
<povik> 20:06 < lofty> But the priority cut algorithm is surprisingly simple when you have sufficient expressive power to say what without saying how
<povik> well not all of us have learned Rust yet :p
<lofty> It's probably expressible with C++20 ranges?
<lofty> [19:07:10] povik: is that something they use extensively in the proprietary compiler? <--- dunno; it's proprietary :p
<lofty> [19:06:59] povik: i suppose there's a paper somewhere that discusses the benefits of majority-inverters <--- "quantum dot cellular automata" is the main reason to consider it
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<xiretza[m]1> Catherine: ^
<xiretza[m]1> they're making the rounds, I'd recommend investing in a mjolnir
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<Wanda[cis]> sigh.
<Wanda[cis]> ... oh ffs the op status doesn't propagate like that in plumbed rooms?
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<Wanda[cis]> oh. I'm already an admin here. that'd have been good to know.
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<Adrien[m]> <lofty> "Don't look at it, it's a..." <- Patent minefield, could you elaborate ?
<Adrien[m]> AFAIK plenty of scientific papers are public since decades about maj gates
<Adrien[m]> Doing logic opt on netlists represented with maj gates, conversion to/from maj gates representation, digital gates for CMOS, etc
<tpb> Title: US10394988B2 - Majority logic synthesis - Google Patents (at patents.google.com)
<lofty> so, no, logic optimisation on netlists represented with majority gates is patented
<Adrien[m]> The method that is patented is quite specific
<lofty> you mean, using the rules of majority logic to optimise it?
<lofty> which is...incredibly general
<Adrien[m]> Obviously no one would win against an army of lawyers highly skilled to that game
<Adrien[m]> Only thing that is supposed to be patentable would be, one algorithmic way of implementing in software a process that does simplfications
<Adrien[m]> My feeling is you can't patent what is precisely the spec of the behaviour of the maj gate
<Adrien[m]> ok i looked at US20160350469A1
<Adrien[m]> the process of converting a netlist to maj representation, apply optim, convert back to original gates : that is patented
<Adrien[m]> what a shame
<Adrien[m]> that is patenting the intent of a thing... poor world
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