whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<builderdev212> I'm a bit new to yosys. I've used icarus/verilator to simulate verilog before and have played around with GHDL some, and have been looking into yosys because of the ghdl plugin. Is it possible to simulate both vhdl and verilog together? I've seen some work around simulating a vhdl module with a verilog top module, however the project i'm working to
<builderdev212> simulate has a verilog internal module that's called by my vhdl module. Is simulating this even possible? Or should I look into some other method of simulation?
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