02:29 <cr1901> >Info: Running timing-driven placement optimisation...

02:29 <cr1901> Is this a new string in nextpnr?

05:37 <tnt> cr1901: huh no ?

05:57 <tnt> So huh ... even the "good" sim doesn't look all that good when compared with behavioral (like using all source .v) : https://i.imgur.com/KKlVH6b.png

05:58 <tnt> At least "latched_store" is present so at least the cpu doesn't seem to mind.

06:32 <tnt> FWIW, I've confirmed on hw with a logic analyzer that the working/non-working case look indeed like the sim results above.

07:00 <tnt> So, the difference between behavioral & "good" seem to be solved by using a more recent yosys to pre-build pcpi_mul block. (I had used the first failing revision previously). Confirmed both in sim and on real hw.

07:00 <tnt> (summary, now behavioral = synth good and synth bad = missing latched_store)

07:45 <tnt> removing (* parallel_case *) there https://github.com/cliffordwolf/picorv32/blob/master/picorv32.v#L331 fixes the issue. (or rather doesn't exhibit it anymore)

07:45 <tpb> <https://x0.no/4uxpu> (at github.com)

08:25 <tnt> Boiled it down to a reproducer in 50 lines of verilog ... https://pastebin.com/NijQ0nz1

08:25 <tpb> Title: `default_nettype nonemodule mini_dut( input wire pcpi_wr, input - Pastebin.com (at pastebin.com)

08:25 <tnt> You synth mini_dut_wrap_bad you get the output optimized to 1'b0 (which is wrong). You synth mini_dut_wrap_good, you get the correct logic.

08:27 <gatecat> nice, good work!

08:29 <tnt> Tx. Creating an issue now with required file / Makefile to reproduce easily.

08:46 <tnt> Note that the commit I pointed to earlier (new DFF OPT pass) has nothing to do with it ... it just made better DFF optimization and realized the two FF were the same and so used the same one for both signals, triggering this bug.

08:47 <tnt> mwk: so you're in the clear :p

08:55 <tnt> https://github.com/YosysHQ/yosys/issues/2824

09:13 <tnt> I'm going to go with OPT_MUXTREE ... this looks suspicious "Replacing known input bits on port B of cell $flatten\dut_I.$procmux$427: { \pcpi_wr 1'0 } -> 2'00"

09:13 <gatecat> yeah

09:51 <mwk> oh joy

09:51 <mwk> okay, good

09:51 <mwk> I was looking for an excuse to replace opt_muxtree with something much more powerful

09:53 <mwk> ohhh wait, it involves parallel_case

09:54 <mwk> ... parallel_case with one input 0, that shouldn't matter

09:55 <tnt> yeah, and if you remove that '0' input ... it works.

10:03 <gatecat> https://github.com/YosysHQ/yosys/blob/master/passes/opt/opt_muxtree.cc#L375-L376 looks questionable, port_off/port_idx won't be updated for constant inputs, I think

10:03 <tpb> <https://x0.no/4uxq9> (at github.com)

10:03 <gatecat> don't fully understand its logic though

10:04 <mwk> yeah, definitely suspect

10:04 <mwk> hm

10:04 <mwk> that'd be an easy fix though

10:11 <gatecat> mwk: how does https://github.com/YosysHQ/yosys/pull/2825 look ?

10:12 <mwk> gatecat: ... just wrote the exact same thing

10:12 <gatecat> oops

10:12 <mwk> but yeah, looks fine

10:12 <mwk> except it may merit a regression test

10:13 <mwk> which I'm writing right now

10:16 <mwk> gatecat: how about throw in https://gist.github.com/mwkmwkmwk/2a77e94f1194ebfe9822394899c64f63 as tests/opt/bug2824.ys ?

10:17 <tpb> <https://x0.no/4uxqb> (at gist.github.com)

10:17 <gatecat> sure, do you want to push it to that branch?

10:17 <mwk> hmm

10:17 <mwk> right, this is just a branch in the main repo, I can check it out and push it, correct?

10:18 <gatecat> yeah

10:18 <mwk> gatecat: also your PR is missing "Fixes #2824" in the description

10:18 <gatecat> updated, thanks

10:19 <mwk> I pushed the commit

11:05 <mwk> gatecat: i think the PR is ready to merge?

11:07 <gatecat> mwk: yep done

11:07 <mwk> good :)

11:13 <tnt> Damnit, I built yosys last week but the name/email change triggers a full tree rebuild.

11:15 <mwk> welp

11:15 <mwk> ... every day spent developing yosys I'm more happy about my decision to get a ryzen last fall

11:54 <tnt> gatecat / mwk: Just confirmed the fix (on all intermediate testbenches I had and on the actual hardware/project I was originally working on).

11:54 <tnt> Thanks !

12:05 <mwk> great, thanks for the report and diagnosis

12:05 <mwk> !