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<rburton>
Bit of a long short but our fvp-base uboot using vexpress_aemv8a_semi_defconfig worked fine with 2021.10, but since upgrading to 2022.01 the console log stops as TF-A hands over to U-Boot. Are there any known issues?
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<apritzel_>
rburton: thanks for the report, I will have a look ...
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<apritzel_>
so for the sake of the community: rburton and I talked about this privately: CRC32 instructions are the culprit
<apritzel_>
commit 270f8710f92f enabled them by default
<apritzel_>
and it seems like the model is really the only ARMv8 implementation on the planet without them ;-)
<kettenis>
raspberry pi 3/4 have CRC32?
<apritzel_>
at least by default, of course there is a command line option to enable them, which is one way to fix that
<apritzel_>
kettenis: CRC32 yes, but not SHA
<apritzel_>
that's separate
<apritzel_>
the Cortex-A53 TRM says they are always built-in, whereas you can configure the availability of SHA & friends
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<xypron>
mps: I just sent out 3 patches for running the sandbox with musl. Could you, please, test them on a native system ./u-boot -D -l should bring up an X11 window for U-Boot.
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<mps>
xypron: sure, I will try later today/evening
<mps>
xypron: I don't know about these 'fine points' of termios use, so I trust you
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<xypron>
mps: https://tpaste.us/w14a looks like a false positive to me. I cannot find any path to the print statement where dname is not initialized and target_temp is not NULL.
<apritzel>
sjg1: regarding lowlevel_init: sunxi uses it, and according to the README and comments in there it shouldn't
<apritzel>
sjg1: I am looking into what it takes to remove it, but wanted to know if it's worth it (don't fix what ain't broken ...)
<apritzel>
sjg1: but it looks like it has to potential to clean up and simplify things
<mps>
xypron: well, warning says 'maybe' so you are probably right, and no one reported any bug about this (and I didn't had it) to alpine afaik
<sjg1>
apritzel: I am not sure how valuable it is to clean up. That feature used to be quite common (with assembler code) but we have moved away from it
<sjg1>
apritzel: Which code are you looking at?
<apritzel>
it came up because we need to copy from cpu/armv7 to cpu/arm926, to support those ARM9 Allwinner SoCs
<apritzel>
and it looks like we can do the setup in the normal SPL code
<sjg1>
apritzel: Oh I see. It seems like a nice clean-up, but I'll have to leave it to you to decide
<apritzel>
for instance we do clock and pinmux setup there (in the s_init() C function), which IIUC correctly is out of scope
<apritzel>
sjg1: thanks, I am about to have a look, will let you know
<sjg1>
apritzel: Yes that really should be a clock driver, even if it is hacked into an exported spl_.. function there
<apritzel>
agreed, I am wading through the bits to see what's being called when and where, exactly
<apritzel>
we need to sort that out for the RISC-V support anyway