10:42 <cyndis> digetx: I don't expect to have time for anything significant for the rest of the year, but from next year I think it should be better.. hopefully

10:43 <cyndis> fwiw, I have a functional patch series for getting rid of the intr code and using fences for everything but it needs some more time to finish up which I haven't had yet

10:44 <cyndis> regarding the submit latency, I've benchmarked that myself on T186 and seeing pretty consistent ~60us. maybe there's something in allocation/mapping that's magnitudes slower on older chips then?

14:07 <digetx> I will try to create something and send to ML, so we could have a concrete discussion, so far this was and remains the most productive way of working on upstream

14:10 <digetx> indeed, I should try to profile DMA API; it always made me curious why it's so slow, but never got around to profile it

18:33 <maxnet[m]> <digetx> "maxnet: please show me output of..." <- I was able to retrieve the output

18:33 <maxnet[m]> Let me know if you need more or something else

20:42 <digetx> maxnet[m]: thanks, I'll take a look