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<RockBoynton[m]> has anyone figured out how to effectively organize both std and no_std apps and no_std libs in a monorepo such that rust-analyzer can work across all crates? I've been pulling my hair out trying to figure out how to make this work (well I would be if I had any hair left)
<JamesMunns[m]> tbh, I usually just "don't". I use separate editor windows for the std side and the no_std side
<JamesMunns[m]> it seems to handle common path deps well still
<RockBoynton[m]> I feared that would be the answer. It is just a bummer when you do something like "goto definition" and make some edits and then only later realize in CI that your edits actually hit a clippy lint.
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<thejpster[m]> Well I think I got code running on my R9A02G021 board, but only once.
<thejpster[m]> It won't program after that. I wonder if it's an ECC RAM issue. There's a note on the SEGGER Wiki that the ECC RAM requires initialisation. I'm going to try the example project in SEGGER Embedded Studio and see if maybe it pokes some registers to set the chip up before it tries to put the flashloader blob into RAM.
<thejpster[m]> My thinking is that it had some code on it that configured the chip, but I replaced that code, and then I hard power cycled the board and now it doesn't work.
<thejpster[m]> hmm, Embedded Studio just crashes when you try and debug the application. Perhaps because it just shells out to JFlash and that cannot connect.
<thejpster[m]> I think I broke it.
<bitts[m]> Not familiar with that chip, but normally there is some way to erase chip and upload original fw at least? There might be hoops, but possible?
<thejpster[m]> J-Link just cannot connect to the target any more
<bitts[m]> Does connect under reset work?
<thejpster[m]> > Trying again with connect under reset (ndmreset-bit)
<bitts[m]> Ah. Any boot modes you can mess around with (through some pins or something)?
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<thejpster[m]> Not that I can see. Holding the reset button didn’t help either.
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