00:08 <adamgreig[m]> even on a cortex-m7 with the worst-case scenario of an interrupt handler that just writes to an address in sram and a main that just loops cpsid, pend interrupt, cpsie, ldr that address I always observe the interrupt's write, hmmm

00:10 <adamgreig[m]> https://gist.github.com/adamgreig/446806a96f46490832ffaadf651b35d8

01:54 <JamesMunns[m]> <adamgreig[m]> "even on a cortex-m7 with the..." <- does it need to be in some cached memory to work? like do you need to enable dcache or be using some specific region for that to potentially not be "basically a volatile"?

14:36 <firefrommoonligh> PSA: CAN termination resistors are not optional

15:58 <Dr_Viper[m]> I am new here how to start from scratch

16:00 <K900> https://docs.rust-embedded.org/book/

16:17 <Dr_Viper[m]> Okay