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<@matt:ucc.asn.au> does anyone have a good example of CI testing a crate only uses alloc when "alloc" feature is enabled? seems more of a hassle than checking for no_std, since it only fails at link stage
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<@ryan-summers:matrix.org> @dirb
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<@ryan-summers:matrix.org> : Thanks for the inspiration to finally get this finished up! :) https://reviews.llvm.org/D152626 - hopefully we can get stack probing integrated in rustc for ARM to alleviate these stack overflow issues quicker
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<@ryan-summers:matrix.org> Just compiling LLVM locally caused by disk space to disappear and my 32 GB of RAM to overflow.... And I thought Rust builds were bad
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<@romancardenas:matrix.org> I pushed a new version of "riscv" peripherals with the "unsafe new(...)" but safe "read(...)"/"write(...)" approach: https://github.com/rust-embedded/riscv/pull/135
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I personally like this approach a lot, but I found some conceptual issue that deserves further discussion:
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Without context, a register just stores a buch of 0s and 1s so I can safely "write" on them. However, if the register happens to contain the priority threshold of my interrupt controller, then changing the threshold from 7 to 4 may break a critical section, and thus should be marked as "unsafe".
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Currently, I can change the priority threshold of the PLIC either with the safe "write(self, u32)" function (i.e., no context about what the register is about) or with the "unsafe fn set_threshold<P: PriorityNumber>(self, P)" function (i.e., I know what the peripheral is about and thus I need to be careful).
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I personally like this concept, but it would be great if we discuss it further in the next meeting to come up with a more robust design pattern.
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Have a good weekend!
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