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<re_irc> <@nihal.pasham:matrix.org> reaching out to the broader community in case anyone has come across a similar issue -
<re_irc> https://matrix.to/#/!ilYBHdZNkWoALhBMSx:matrix.org/$cLKZB-Fkmlc-GbxcPyHI0xHtTjDRFBGy1KrpaYwTHcs?via=matrix.org&via=afofo.com&via=conduit.electromatic.us
<re_irc> any inputs would be great..
<re_irc> <@nihal.pasham:matrix.org> reaching out to the broader community in case anyone has come across a similar issue - https://matrix.to/#/!ilYBHdZNkWoALhBMSx:matrix.org/$cLKZB-Fkmlc-GbxcPyHI0xHtTjDRFBGy1KrpaYwTHcs?via=matrix.org&via=afofo.com&via=conduit.electromatic.us
<re_irc> any inputs would be great..
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<re_irc> <@hyahoos:matrix.org> I know this has been asked many times
<re_irc> <@hyahoos:matrix.org> but im still wondering are we really not gnna add non-blocking traits to our IO? for example non-blocking I2c communication?
<re_irc> <@jannic:matrix.org> There is embedded-hal-async. But I guess you are looking for non-blocking non-async traits?
<re_irc> <@hyahoos:matrix.org> ya
<re_irc> <@hyahoos:matrix.org> that
<re_irc> <@jannic:matrix.org> I'm not completely sure but my impression is that most people working on embedded-hal are preferring async when they need non-blocking. So there's just nobody left caring much about embedded-hal-nb.
<re_irc> <@jannic:matrix.org> It's unfortunate that many interesting async features still need nightly rust.
<re_irc> <@hyahoos:matrix.org> alright then, thanks
<re_irc> <@hyahoos:matrix.org> yeah I just realized I could instead try to do embassy-hals and do async and stuff like that to get no-blocking behaviour
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<re_irc> <@9names:matrix.org> : could you summarise the issue here first? it's quite the ask to get folks to join a new channel and read a paragraph of prose to find out what your issue is and if they have relevant experience that could help you.
<re_irc> <@9names:matrix.org> it's especially opaque since matrix doesn't even tell you which room you're linking to, so there's zero context for your request
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<re_irc> <@nihal.pasham:matrix.org> ah ok
<re_irc> <@nihal.pasham:matrix.org> I've been working on adding Rust support for the i.MX 8M nano and managed to get the board up and running along with a working uart driver - code here (https://github.com/nihalpasham/rustBoot/tree/main/boards/bootloaders). The next step in my plan is to add a uSDHC driver for the nano. Here's a link to the initial implementation...
<re_irc> ... (https://github.com/nihalpasham/rustBoot/blob/main/boards/hal/src/nxp/imx8mn/bsp/drivers/usdhc.rs). Though the implementation keeps throwing some i.MX specific uSDHC command errors. I was hoping someone here can shed some light on what I'm missing.
<re_irc> The sequence of steps I used are as follows
<re_irc> - enable the usdhc2 clocks via the ccm peripheral,
<re_irc> - set mux state for the uSDHC2 peripheral via the iomuxc peripheral
<re_irc> So far, steps 1 and 2 seem to work (I think)
<re_irc> - initialize uSDHC driver and send a couple of commands to verify we have a working driver
<re_irc> Here's the debug log output. From what I gather by looking at the contents of the uSDHC's _interrupt status_ field (i.e. a value of 0x00048001), the command (i.e. SEND_IF_CMD) was successfully sent and a response was received, however the response returned contains an error - *command end bit error*. Not entirely sure why this is happening.
<re_irc> Also the _present status_ register has the SDOFF bit set (SD clock gated off internally). Again not sure why this is happening. The reference manual doesn't provide more information about these bits or the errors.
<re_irc> Any inputs would be greatly appreciated. Please let me know if more information is required.
<re_irc> [ 0.000004] imx8mn-rs version 0.1.0
<re_irc> [ 0.003516] Booting on: i.MX 8M Nano EVK
<re_irc> [ 0.007340] Current privilege level: EL3
<re_irc> [ 0.011254] Exception handling state:
<re_irc> [ 0.014966] Debug: Masked
<re_irc> [ 0.018166] SError: Unmasked
<re_irc> [ 0.021464] IRQ: Masked
<re_irc> [ 0.024758] FIQ: Masked
<re_irc> [ 0.027968] Drivers loaded:
<re_irc> [ 0.030739] 1. i.MX8M Uart2
<re_irc> [ 0.034045] Chars written: 382
<re_irc> [ 0.036995] Sd host circuit reset..
<re_irc> [ 0.040462] Prescaler = 4, Divisor = 15, Freq Set = 400000
<re_irc> [ 0.045966] Sd: sending command, CMD_NAME: "GO_IDLE_STATE", CMD_CODE: 0x00000000, CMD_ARG: 0x00000000
<re_irc> [ 0.056378] Sd: sending command, CMD_NAME: "SEND_IF_COND", CMD_CODE: 0x08020000, CMD_ARG: 0x000001aa
<re_irc> [ 0.066602] Sd Error: Cmd response returned an error, PresentStatus: 0xf0048088, intStatus: 0x00048001, Resp0: 0x00000000, timeDiff: 0
<re_irc> [ 0.078923] Sd host circuit reset..
<re_irc> [ 0.082293] Prescaler = 4, Divisor = 15, Freq Set = 400000
<re_irc> [ 0.087788] Sd: sending command, CMD_NAME: "GO_IDLE_STATE", CMD_CODE: 0x00000000, CMD_ARG: 0x00000000
<re_irc> [ 0.098218] Sd: sending command, CMD_NAME: "APP_CMD", CMD_CODE: 0x17000000, CMD_ARG: 0x00000000
<re_irc> [ 0.108176] Sd: sending command, CMD_NAME: "APP_SEND_OP_COND", CMD_CODE: 0x09020000, CMD_ARG: 0x00ff8000
<re_irc> [ 0.119630] Sd Error: Cmd response returned an error, PresentStatus: 0xf0048088, intStatus: 0x00048001, Resp0: 0x00000000, timeDiff: 0
<re_irc> [ 0.131839] Sd Error: ACMD41 returned non-timeout error SdError
<re_irc> [ 0.137829] uSDHC: PRES_STATE: 0xf0048088, SYS_CTRL: 0x000e02e0, INT_STATUS: 0x00048001
<re_irc> [ 0.146063] uSDHC: CMD "APP_SEND_OP_COND", resp: SdError, CMD_RSP3: 0x00000000, CMD_RSP2: 0x00000000, CMD_RSP1: 0x00000000, CMD_RSP0: 0x00000000
<re_irc> [ 0.159382] failed to initialize
<re_irc> [ 0.162494]
<re_irc> [ 0.164107] ... wait forever
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<re_irc> <@nihal.pasham:matrix.org> ah ok, didn't know that. assumed matrix just works if its an internal channel, guess not
<re_irc> <@nihal.pasham:matrix.org> ah ok, didn't know that. assumed matrix just works if its another matrix channel, guess not
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<re_irc> <@thejpster:matrix.org> Do you have a working C example to crib from? I'm not sure many folks here have done much Cortex-A, never mind iMX8
<re_irc> <@ryan-summers:matrix.org> Is there a crate for mocking embedded-hal devices for purposes of demonstrating usage of a driver in rust-doc?
<re_irc> <@ryan-summers:matrix.org> embedded-hal-mock exists, but it looks like it's more geared towards unit testing of drivers (i.e. you have to provide expected SPI transactions etc.)
<re_irc> <@jamesmunns:beeper.com> Not that I'm aware, but you totally could just do a quick impl that returns Ok() for everything
<re_irc> <@ryan-summers:matrix.org> I just want a dummy module that doesn't do anything, but impls the traits
<re_irc> <@ryan-summers:matrix.org> Yeah was hoping to avoid the boilerplate, but it's not too bad tbh
<re_irc> <@ryan-summers:matrix.org> I only need SPI and CS
<re_irc> <@jamesmunns:beeper.com> with R-A you can write "impl Trait for FakeType { }" then do an "implement missing members" autofill
<re_irc> <@nihal.pasham:matrix.org> : I'm relying on u-boot (https://github.com/nxp-imx/uboot-imx) which is like a defacto standard for cortex-a bootloaders and arm-trusted-firmware (https://github.com/ARM-software/arm-trusted-firmware) repos for now.
<re_irc> <@jamesmunns:beeper.com> which will give you "todo!()"s in everything
<re_irc> <@ryan-summers:matrix.org> Oh nice, I'll get that a shot then
<re_irc> <@jamesmunns:beeper.com> : Do they have an SDCard example? I think that was what JP was getting at
<re_irc> <@jamesmunns:beeper.com> like, "look at what the C code does to make sure you haven't missed any setup steps"
<re_irc> <@nihal.pasham:matrix.org> yeah, I've cross-checked my impl with that of uboot and others. Their impls are similar if not exactly the same (at least as far the sd-card initialisation routine).
<re_irc> to cross-check, I compiled uboot (and the corresponding device-tree) for the i.mx8 board. It works as expected but somehow fails when I use my impl and apply the same settings
<re_irc> <@nihal.pasham:matrix.org> For more context from the other thread:
<re_irc> I used the (exact) same "pad ctrl" settings as the ones from the linux device tree in "imx8mn.dtsi" and I am now able to detect and report if an sd-card is inserted. But I still cant figure out what's causing the command error (i.e. CEBE bit error).
<re_irc> [ 71.987092] imx8mn-rs version 0.1.0
<re_irc> [ 71.994481] Current privilege level: EL3
<re_irc> [ 71.990506] Booting on: i.MX 8M Nano EVK
<re_irc> [ 72.002008] Debug: Masked
<re_irc> [ 71.998294] Exception handling state:
<re_irc> [ 72.005139] SError: Unmasked
<re_irc> [ 72.008524] IRQ: Masked
<re_irc> [ 72.011811] FIQ: Masked
<re_irc> [ 72.014926] Drivers loaded:
<re_irc> [ 72.017677] 1. i.MX8M Uart2
<re_irc> [ 72.020958] Chars written: 382
<re_irc> [ 72.023983] Sd host circuit reset..
<re_irc> [ 72.027439] card inserted...
<re_irc> [ 72.030367] Prescaler = 4, Divisor = 15, Freq Set = 400000
<re_irc> [ 72.035865] Sd: sending command, CMD_NAME: "GO_IDLE_STATE", CMD_CODE: 0x00000000, CMD_ARG: 0x00000000
<re_irc> [ 72.049859] Sd: sending command, CMD_NAME: "ALL_SEND_CID", CMD_CODE: 0x02010000, CMD_ARG: 0x00000000
<re_irc> [ 72.065140] Sd Error: Cmd response returned an error, VendSpec: 0x2000f800, ProtCtrl: 0x00800040, PresentStatus: 0xf00d8088, intStatus: 0x00048001, Re
<re_irc> sp0: 0x00000000, timeDiff: 5062
<re_irc> [ 72.081495] uSDHC: PRES_STATE: 0xf00d8088, SYS_CTRL: 0x000e02ef, INT_STATUS: 0x00048001
<re_irc> [ 72.089641] uSDHC: CMD "ALL_SEND_CID", resp: SdError, CMD_RSP3: 0x00000000, CMD_RSP2: 0x00000000, CMD_RSP1: 0x00000000, CMD_RSP0: 0x00000000
<re_irc> [ 72.102677] failed to initialize
<re_irc> [ 72.105781]
<re_irc> [ 72.107302] ... wait forever
<re_irc> On a side note, I noticed that one of the pins in the device tree is referenced as uSDHC2's voltage regulator (i.e. pad "iomuxc_sw_mux_ctl_pad_sd2_reset_b") but its pinmux configuration uses a mux mode that doesn't make sense. The device-tree contains a mux mode of 0x5 for this pin instead of a 0. Would anyone know why?
<re_irc> When I set the pin’s mux-mode to 0x5 the "usdh controller" simply times out i.e. it doesn’t even detect the card.
<re_irc> *Device tree source for the usdhc2’s voltage regular:*
<re_irc> reg_usdhc2_vmmc: regulator-usdhc2 {
<re_irc> compatible = "regulator-fixed";
<re_irc> pinctrl-names = "default";
<re_irc> pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
<re_irc> regulator-name = "VSD_3V3";
<re_irc> regulator-min-microvolt = <3300000>;
<re_irc> regulator-max-microvolt = <3300000>;
<re_irc> gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
<re_irc> off-on-delay-us = <12000>;
<re_irc> enable-active-high;
<re_irc> };
<re_irc> &usdhc2 {
<re_irc> assigned-clock-rates = <200000000>;
<re_irc> assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
<re_irc> pinctrl-names = "default", "state_100mhz", "state_200mhz";
<re_irc> pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
<re_irc> pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
<re_irc> pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
<re_irc> cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
<re_irc> bus-width = <4>;
<re_irc> vmmc-supply = <&reg_usdhc2_vmmc>;
<re_irc> status = "okay";
<re_irc> };
<re_irc> pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
<re_irc> fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41>;
<re_irc> };
<re_irc> *Device tree binary for the usdhc2 voltage regulator :*
<re_irc> regusdhc2vmmcgrp {
<re_irc> fsl,pins = <0xec 0x354 0x00 0x05 0x00 0x41>;
<re_irc> u-boot,dm-spl;
<re_irc> phandle = <0x42>;
<re_irc> };
<re_irc> regulator-usdhc2 {
<re_irc> compatible = "regulator-fixed";
<re_irc> pinctrl-names = "default";
<re_irc> pinctrl-0 = <0x42>;
<re_irc> regulator-name = "VSD_3V3";
<re_irc> regulator-min-microvolt = <0x325aa0>;
<re_irc> regulator-max-microvolt = <0x325aa0>;
<re_irc> gpio = <0x26 0x13 0x00>;
<re_irc> enable-active-high;
<re_irc> u-boot,off-on-delay-us = <0x4e20>;
<re_irc> phandle = <0x2d>;
<re_irc> };
<re_irc> mmc@30b50000 {
<re_irc> compatible = "fsl,imx8mn-usdhc\0fsl,imx8mm-usdhc\0fsl,imx7d-usdhc";
<re_irc> reg = <0x30b50000 0x10000>;
<re_irc> interrupts = <0x00 0x17 0x04>;
<re_irc> clocks = <0x02 0x56 0x02 0x4d 0x02 0xaf>;
<re_irc> clock-names = "ipg\0ahb\0per";
<re_irc> fsl,tuning-start-tap = <0x14>;
<re_irc> fsl,tuning-step = <0x02>;
<re_irc> bus-width = <0x04>;
<re_irc> status = "okay";
<re_irc> assigned-clocks = <0x02 0x68>;
<re_irc> assigned-clock-rates = <0xbebc200>;
<re_irc> pinctrl-names = "default\0state_100mhz\0state_200mhz";
<re_irc> pinctrl-0 = <0x29 0x2a>;
<re_irc> pinctrl-1 = <0x2b 0x2a>;
<re_irc> pinctrl-2 = <0x2c 0x2a>;
<re_irc> cd-gpios = <0x23 0x0f 0x01>;
<re_irc> vmmc-supply = <0x2d>;
<re_irc> u-boot,dm-spl;
<re_irc> sd-uhs-sdr104;
<re_irc> sd-uhs-ddr50;
<re_irc> };
<re_irc> <@nihal.pasham:matrix.org> * _For more context from the other thread:_
<re_irc> <@thejpster:matrix.org> Sorry, I don't know anything about the iMX8.
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<re_irc> <@firefrommoonlight:matrix.org> Hi! What is y'alls take on maintaining a system time uptime count / timestamp? From what I've seen in C, a cortex-m interrupt tick is common. This seems to be a bit awk as it's bothering the CPU frequently. Alternatives include a dedicated RTC peripheral, and hardware timers. Obviously if you want accurate time and dates over long periods, RTC w/dedicated Xtal is the way to go. For generating CAN network timestamps...
<re_irc> ... etc, this is what I've set up. I'm posting to see what y'all think vice alternatives, and why the Systick approach is so common in OSS c code bases:
<re_irc> // We use a hardware counter to measure relative system time. This is the number of times
<re_irc> // it has overflowed. (timer expired)
<re_irc> /// Example use, to get seconds since start: `tick_count_fm_overflows_s() +
<re_irc> pub static TICK_OVERFLOW_COUNT: AtomicU32 = AtomicU32::new(0);
<re_irc> const TICK_TIMER_PERIOD: f32 = 0.5; // in seconds. Decrease for higher measurement precision.
<re_irc> /// tick_timer.time_elapsed().as_secs()`
<re_irc> pub fn tick_count_fm_overflows_s() -> f32 {
<re_irc> TICK_OVERFLOW_COUNT.load(Ordering::Acquire) as f32 * TICK_TIMER_PERIOD
<re_irc> }
<re_irc> <@firefrommoonlight:matrix.org> Basically, at a low frequency (in this case, 2 Hz), the overflow count interrupt fires, incrementing a counter; then it's just a matter of reading the counter, and reading the timer current value. Interrupt, which runs much slower than a systick would:
<re_irc> #[task(binds = TIM5, shared = [tick_timer], local = [], priority = 1)]
<re_irc> fn tick_isr(mut cx: tick_isr::Context) {
<re_irc> // todo: Do this without locking.
<re_irc> cx.shared.tick_timer.lock(|timer| {
<re_irc> /// Increments the tick overflow.
<re_irc> timer.clear_interrupt(TimerInterrupt::Update);
<re_irc> });
<re_irc> // (*pac::TIM5::ptr())
<re_irc> TICK_OVERFLOW_COUNT.fetch_add(1, Ordering::Relaxed);
<re_irc> }
<re_irc> <@firefrommoonlight:matrix.org> Basically, at a low frequency (in this case, 2 Hz), the overflow count interrupt fires, incrementing a counter; then it's just a matter of reading the counter, and reading the timer current value. Interrupt, which runs much slower than a systick would:
<re_irc> #[task(binds = TIM5, shared = [tick_timer], local = [], priority = 1)]
<re_irc> /// Increments the tick overflow.
<re_irc> fn tick_isr(mut cx: tick_isr::Context) {
<re_irc> cx.shared.tick_timer.lock(|timer| {
<re_irc> // todo: Do this without locking.
<re_irc> timer.clear_interrupt(TimerInterrupt::Update);
<re_irc> });
<re_irc> TICK_OVERFLOW_COUNT.fetch_add(1, Ordering::Relaxed);
<re_irc> }
<re_irc> <@firefrommoonlight:matrix.org> (Using a HAL-level helper fn that gets timer elapsed time since last overflow or since start)
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