02:13 <re_irc> < (@firefrommoonlight:matrix.org)> : I just upgraded and am about to try

02:13 <re_irc> < (@firefrommoonlight:matrix.org)> Rel: How to you setup the dcache? https://docs.rs/cortex-m/latest/cortex_m/peripheral/struct.SCB.html#method.enable_dcache

02:13 <re_irc> < (@firefrommoonlight:matrix.org)> Ie, how do you get CPUID?

02:18 <re_irc> < (@firefrommoonlight:matrix.org)> Flashes/runs fine, btw

02:22 <re_irc> < (@jbeaurivage:matrix.org)> Hi all, I'm trying to implement an async API for SPI transfers with DMA, but I'm struggling to get it right. Wondering if some of you have advice/if I've overlooked something.

02:23 <re_irc> < (@firefrommoonlight:matrix.org)> async/await, or non-blocking?

02:23 <re_irc> < (@firefrommoonlight:matrix.org)> What MCU?

02:24 <re_irc> < (@jbeaurivage:matrix.org)> async/await on SAM MCUs. Specifically, testing on an ATSAMD51. From what I understand, writing to the chip's DATA register clocks a byte on the MOSI line, and the slave simultaneously sends back a byte on MISO. I think I'm struggling to get the futures to poll in the right order, but debugging is pretty hard.

02:26 <re_irc> < (@jbeaurivage:matrix.org)> Here's the bit that's supposed to launch the transfers:

02:26 <re_irc> write_res.and(read_res).map_err(Error::Dma)?;

02:26 <re_irc> let tx_fut = write_dma::<_, S>(&mut self._rx_channel, spi_ptr.clone(), source);

02:26 <re_irc> let (write_res, read_res) = futures::join!(rx_fut, tx_fut);

02:26 <re_irc> let rx_fut = read_dma::<_, S>(&mut self._tx_channel, spi_ptr, sink);

02:28 <re_irc> < (@jbeaurivage:matrix.org)> My logic is that the RX channel should be polled first, and would stall until bytes actually start coming in. Then TX should be polled, which will get MOSI and SCK going. In reality I don't think that's what's happening

02:36 <re_irc> < (@firefrommoonlight:matrix.org)> Dcache sorted: "cp.SCB.enable_dcache(&mut cp.CPUID);"

02:37 <re_irc> < (@firefrommoonlight:matrix.org)> Although:

02:37 <re_irc> "cortex_m::peripheral::SCB::icache_enabled()" and dcache_enabled() are showign false, even after setting them in "cortex_m", and in the STM32 FLASH_ACR reg

02:46 <re_irc> < (@firefrommoonlight:matrix.org)> Is there any reason (other than perhaps slightly increased power use) to not enable the data cache, instruction cache, and prefetch on Cortex-M4? Of note, I'm a bit fuzzy on how the STM32 FLASH_ACR register setting for this value interacts with the "cortex_m" features

02:47 <re_irc> < (@firefrommoonlight:matrix.org)> AFAIK they're present on some Cortex-M4s but not others, but are fundamentally more of an ARM than STM32 thing?

03:19 <re_irc> < (@9names:matrix.org)> : Good way to check if your memory corruption is due to cache coherence issues I guess?

03:21 <re_irc> < (@firefrommoonlight:matrix.org)> Thx

03:21 <re_irc> < (@firefrommoonlight:matrix.org)> Also of note, the FLASH_ACR (STM32 regs for ICACHE and DCACHE, as well as prefetch) are staying set, but the cortex-M ones aren't

03:21 <re_irc> < (@firefrommoonlight:matrix.org)> I'm also a bit unclear if maybe the cortex-m ones are just for M7?

07:40 <re_irc> < (@adamgreig:matrix.org)> Yea, cm4 doesn't have icache or dcache, they're cm7

07:40 <re_irc> < (@adamgreig:matrix.org)> Which is probably why icache_enabled is returning false

07:41 <re_irc> < (@adamgreig:matrix.org)> FLASH_ACR is a totally separate ST thing to do with reading the flash

07:41 <re_irc> < (@adamgreig:matrix.org)> There's the ST ART which is the flash cache/predictor but iirc is enabled by default

07:44 <re_irc> < (@adamgreig:matrix.org)> (here icache and dcache specifically means the cortex-m internal caches, which are optional for a c-m CPU and never present in cm0/3/4, and always(?) present in cm7; SoC vendors like ST can add other caches outside the core like the ART or other memory system stuff but they're called something else and operated using proprietary mmio regs, not cpu regs)

09:09 <re_irc> <michael.desilva> Hi al,

09:09 <re_irc> Is it incorrect to assume one could do this:

09:09 <re_irc> fn toggle_led<E, T>(pin: &mut T)

09:09 <re_irc> where

09:09 <re_irc> ... long message truncated: https://psion.agg.io/_matrix/media/r0/download/psion.agg.io/XkjxG2cHlAE6mc3d7nCYvKvGm4KdZGXw (26 lines)

09:10 <re_irc> <michael.desilva> +Ofcourse "Gpio14<esp_idf_hal::gpio::Output>" is its own concrete type though.

09:11 <re_irc> <michael.desilva> +I suppose type-erasure via a custom Trait object could also work?

09:26 <re_irc> < (@jaxter184:matrix.org)> at risk of sounding stupid, did it not work to just change "&led_onboard" to "&mut led_onboard"?

09:29 <re_irc> <michael.desilva> nope, the base type is still the same.

09:42 <re_irc> < (@datdenkikniet:matrix.org)> That's not correct: &T != &mut T. I think the error message (in it's entirety, not just the last note) explain what's wrong (which is in line with what jaxter184 is saying)

09:46 <re_irc> < (@datdenkikniet:matrix.org)> Also important to note is that the error occurs at the _call site_, not where you define your function (so your function definition, without knowing the details of ToggleableOutputPin) is most likely fine and should do what you expect it to do

09:47 <re_irc> < (@datdenkikniet:matrix.org)> * function, so your function definition (without

09:49 <re_irc> <michael.desilva> Oh this works " toggle_led::<anyhow::Error, Gpio14<esp_idf_hal::gpio::Output>>(&mut led_onboard);"

09:49 <re_irc> <michael.desilva> * "toggle_led::<anyhow::Error,

09:49 <re_irc> <michael.desilva> I was failing to specify E, T in the caller, and the "&mut" was needed too ofc

09:50 <re_irc> <michael.desilva> Otherwise I would give

09:50 <re_irc> found reference `&Gpio14<esp_idf_hal::gpio::Output>`

09:50 <re_irc> = note: expected mutable reference `&mut Gpio14<esp_idf_hal::gpio::Output>`

09:52 <re_irc> < (@marmrt:matrix.org)> I think you should remove the error completely, as the function doesn't return a "Result<>" it cannot return an error anyway

09:53 <re_irc> < (@marmrt:matrix.org)> Unless there's some error handling in the function not shown

09:53 <re_irc> <michael.desilva> Separate question re. https://github.com/esp-rs/esp-idf-svc/blob/master/src/http/server.rs#L518

09:53 <re_irc> How can I access details of the request?

09:53 <re_irc> // setup http server

09:53 <re_irc> ... long message truncated: https://psion.agg.io/_matrix/media/r0/download/psion.agg.io/1oU6jMhEj2kGU7jxmfdBXLiHUBWA7YXO (7 lines)

09:53 <re_irc> let server_config = HttpServerConfiguration::default();

10:04 <re_irc> < (@datdenkikniet:matrix.org)> That's not correct: &T != &mut T. I think the error message (in it's entirety, not just the last note) explains what's wrong (which is in line with what jaxter184 is saying)

10:07 <re_irc> <michael.desilva> "pub struct EspHttpRequest<'a>(&'a mut httpd_req_t);" should mean I can access the inner .0 right?

10:07 <re_irc> error[E0609]: no field `0` on type `esp_idf_svc::http::server::EspHttpRequest<'_>`

10:07 <re_irc> --> src/main.rs:255:18

10:07 <re_irc> |

10:07 <re_irc> ... long message truncated: https://psion.agg.io/_matrix/media/r0/download/psion.agg.io/ch1iGfSMa0v2XfyExdr7Z2IH9EDH7Os7 (6 lines)

10:08 <re_irc> <michael.desilva> These methods should be available hmm https://github.com/esp-rs/esp-idf-svc/blob/master/src/http/server.rs#L518-L543

10:12 <re_irc> <michael.desilva> Hmm "EspHttpConnection" seems more promising.

10:13 <re_irc> < (@marmrt:matrix.org)> https://esp-rs.github.io/esp-idf-svc/esp_idf_sys/struct.httpd_req.html

10:27 <re_irc> < (@dirbaio:matrix.org)> : is that what the end user would write, or code inside the HAL?

10:28 <re_irc> <michael.desilva> : This is a working example I've referred to https://github.com/ferrous-systems/espressif-trainings/blob/main/intro/http-server/examples/http_server.rs#L29-L36

10:28 <re_irc> <michael.desilva> the server works but I want to access further inner details of the request.

10:28 <re_irc> <michael.desilva> https://github.com/esp-rs/embedded-svc/blob/v0.22.3/src/http/server/registry.rs#L16

11:54 <re_irc> < (@jbeaurivage:matrix.org)> : That's HAL code. I suppose I'm second guessing my use of futures::join here. I'm getting some weird behaviour like interrupts never firing, blocking the rx future from completing

12:10 <re_irc> <michael.desilva> Figured it out. I was missing a trait in my imports to enable Request handling.

12:14 <re_irc> < (@jbeaurivage:matrix.org)> * completing. I'm also pretty sure that the DMA transfers themselves work fine, I've had no problem with UART and SPI DMA transfers

12:14 <re_irc> <michael.desilva> +https://github.com/esp-rs/esp-idf-svc/blob/v0.42.5/src/http/server.rs

12:15 <re_irc> <michael.desilva> The trap I was falling for was looking at the master branch and not the latest release tag. 🤦♂️

12:24 <re_irc> < (@firefrommoonlight:matrix.org)> : Thanks for the explanation!

12:25 <re_irc> < (@firefrommoonlight:matrix.org)> Also of note, the L5 and U5 (M-33) don't have the same ST Flash ACR Dcache, ICache and Prefetch, but a differnet setup

12:26 <re_irc> < (@firefrommoonlight:matrix.org)> It seems these features, whether ST or ARM, seem to fall along CPU divisions

12:27 <re_irc> < (@adamgreig:matrix.org)> ACR is just the access control register btw, not a particular feature of the flash peripheral

12:29 <re_irc> < (@firefrommoonlight:matrix.org)> Oh that makes sense why it's located there!

12:29 <re_irc> < (@firefrommoonlight:matrix.org)> (wait states are there too)

12:30 <re_irc> < (@jaxter184:matrix.org)> oh, wow, that futures crate seems very handy

12:31 <re_irc> < (@jaxter184:matrix.org)> i was trying to write an interrupt-based digital encoder thing, and I ended up with three separate tasks (two to read GPIOs and send a signal to the third, which would do the calculation), but using "futures::select" seems like itd let me use just one

14:29 <re_irc> < (@caemor:matrix.org)> are there any i2s or pdm mics that anyone uses in rust yet? a quick search only revealed the hal-abstraction: https://crates.io/crates/embedded-i2s but without any crates implementing it yet

15:01 <re_irc> < (@firefrommoonlight:matrix.org)> I've been using the ST ones. Lang doesn't matter

15:02 <re_irc> < (@firefrommoonlight:matrix.org)> Which MCU are you using them with?

15:06 <re_irc> < (@firefrommoonlight:matrix.org)> I've been using the ST ones.

16:13 <re_irc> < (@caemor:matrix.org)> its for an riscv pulpissimo platform

16:13 <re_irc> < (@caemor:matrix.org)> * a