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<re_irc> < (@CyReVolt:matrix.org)> https://faultlore.com/blah/fix-rust-pointers/ this?
<re_irc> < (@9names:matrix.org)> Yep
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<re_irc> < (@jamesmunns:beeper.com)> A lot of the core problem is:
<re_irc> - Rust assumes certain things are ALWAYS true (there is never aliasing access to variables)
<re_irc> - Rust assumes certain things about the world before it starts (e.g. statics are initialized)
<re_irc> - Therefore: you can't initialize your own program from within your own program, because it would break one or both of the above statements
<re_irc> < (@jamesmunns:beeper.com)> This is _also_ true in C/C++, for the record
<re_irc> < (@jamesmunns:beeper.com)> so, you COULD write that code in Rust, it just CAN'T be the same "program". e.g. a bootloader could do that initialization for the program it loads, but the program cannot do it itself
<re_irc> < (@jamesmunns:beeper.com)> the reason we usually "fall back" to ASM for this is that ASM has essentially no "environment rules", e.g. there are no invariants to violate, therefore there can be no undefined behavior (i'm sure this statement could be lawyered, but you get the point)
<Darius> isn't that what we have crt0 for?
<Darius> I mean that's what does it for C/C++
<re_irc> < (@jamesmunns:beeper.com)> yes
<re_irc> < (@jamesmunns:beeper.com)> in the old days, we wrote "crt0" in Rust
<re_irc> < (@jamesmunns:beeper.com)> it was decided that this was (at least theoretically) a bad idea
<re_irc> < (@jamesmunns:beeper.com)> now we use inline asm
<re_irc> < (@jamesmunns:beeper.com)> (or global asm? Not sure exactly. But asm inits the world before we get to rust)
<re_irc> < (@jamesmunns:beeper.com)> it's also not uncommon (in C/C++ embedded) projects to see a "startup_$PLATFORM.s" file in the build directories
<Darius> righto
<re_irc> < (@adamgreig:matrix.org)> currently the cortex_m_rt reset vector is a bastardised global_asm, hopefully soon a naked_fn
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<re_irc> < (@lachlansneff:matrix.org)> Naked functions aren’t stable?
<re_irc> < (@adamgreig:matrix.org)> no :(
<re_irc> < (@adamgreig:matrix.org)> there was some hope they'd land the same time as new asm!() but there are various unresolved issues
<re_irc> < (@adamgreig:matrix.org)> the current hope is to stabilise what used to be constrained_naked_fn only, where the only permitted body is a single asm!() call, but that's also not stable yet
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<re_irc> <ilpalazzo-ojiisan> Beg pardon; is there any explanation anywhere regarding what functions are considered “naked”?
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<re_irc> < (@emilgardis:matrix.org)> : good job on all the triaging!
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<re_irc> < (@adamgreig:matrix.org)> ilpalazzo-ojiisan: currently you can't make a naked function in stable rust, it's a proposed new feature. in general a "naked function" is one that is generated with no preamble or postamble instructions, whereas usually the compiler would add a preamble to e.g. save certain registers to the stack and maybe advance the stack pointer to allocate a stack frame for this function's local variables etc, and...
<re_irc> ... undo that on exit as required
<re_irc> < (@adamgreig:matrix.org)> it's useful to be able to write these for very specific circumstances, like interrupt handlers on some platforms (but not on arm where the interrupt handlers expect a normal C ABI function), or in our case the reset vector
<re_irc> < (@adamgreig:matrix.org)> but because there's no preamble, these functions can't e.g. use local variables, so they're very very limited in what they can safely do
<re_irc> < (@rhedgeco:matrix.org)> Hey all. I am having some issues with SPI on an stm32f401. I am trying to write a continuous stream of data over SPI but it seems that there is a gap in the clock cycle every 16 bits, and it drags out one bit for longer. I found a reference to this on the STM forums, but I dont know how to fix this in rust. Any help would be appreciated.
<re_irc> < (@jamesmunns:beeper.com)> (looking...)
<re_irc> < (@jamesmunns:beeper.com)> the stm32f4 is a little different than the f0 you posted about, seems to be related to "TI mode", still looking...
<re_irc> < (@jamesmunns:beeper.com)> Seems to be controlled by the FRF bit in CR2...
<re_irc> < (@jamesmunns:beeper.com)> ...which defaults to "motorola" mode, and the HAL has no way of setting this to TI mode
<re_irc> - Are you using the HAL? Or writing on the PAC yourself?
<re_irc> < (@jamesmunns:beeper.com)> couple of questions:
<re_irc> - Are you running in release mode?
<re_irc> - Are you using DMA? Or how are you sending the chunks of bytes?
<re_irc> < (@rhedgeco:matrix.org)> I am using the hal.
<re_irc> [profile.dev]
<re_irc> My cargo toml settings are as follows:
<re_irc> lto = "thin"
<re_irc> < (@jamesmunns:beeper.com)> Gotta run, but my guess is:
<re_irc> - it's not actually the TI mode here
<re_irc> - DMA'ing a "block" instead of word at a time will likely fix this
<re_irc> - this could be because you are in debug mode (VERY slow in Rust), or the SPI clock is too fast
<re_irc> - it's probably just the software not able to "keep up" with the line rate of the hardware
<re_irc> < (@jamesmunns:beeper.com)> that being said, if you're in release mode (at 64MHz), and only sending at 1MHz, it FEELS like that should be able to keep up
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<re_irc> < (@jamesmunns:beeper.com)> that being said that being said, the HAL is blocking until the send is complete before sending the next byte, so there might just be enough delay to make this apparent (e.g. it is waiting for it to be totally done, instead of ready for the next word)
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<re_irc> < (@jamesmunns:beeper.com)> you could try NOT making it bidi, which might not wait for the read to also complete?
<re_irc> < (@jamesmunns:beeper.com)> https://github.com/stm32-rs/stm32f4xx-hal/blob/master/src/spi/hal_02.rs#L110-L123 shows it blocking on the read to complete before moving on
<re_irc> < (@rhedgeco:matrix.org)> funnily enough making it not bidi makes the gaps happen every byte
<re_irc> < (@jamesmunns:beeper.com)> whew
<re_irc> < (@rhedgeco:matrix.org)> same in release mode
<re_irc> < (@jamesmunns:beeper.com)> yeah, no idea, it's been a bit before I've messed with the STM32F4.
<re_irc> My gut still says "software is doing a weird thing", more than "your hardware is configured wrong", for what its worth
<re_irc> < (@jamesmunns:beeper.com)> You can also try asking in the #stm32-rs:matrix.org room too
<re_irc> < (@jamesmunns:beeper.com)> Sorry I couldn't help more :/
<re_irc> < (@jamesmunns:beeper.com)> (and good luck!)
<re_irc> < (@rhedgeco:matrix.org)> hey thanks for giving it a shot. its a strange problem
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<re_irc> < (@adamgreig:matrix.org)> : pclk1 at 2MHz seems really slow, maybe try running the clocks as fast as they can as a first step?
<re_irc> < (@jamesmunns:beeper.com)> AFK, but if anyone has the RM handy, does the F4 have a FIFO mode?
<re_irc> < (@grantm11235:matrix.org)> It has a one word buffer
<re_irc> < (@grantm11235:matrix.org)> TXE is set as soon as it starts sending a word, you can write another to the data register when that happens
<re_irc> < (@grantm11235:matrix.org)> The HAL impl looks ok
<re_irc> < (@rhedgeco:matrix.org)> it definitely improves the issue
<re_irc> < (@rhedgeco:matrix.org)> but its still present when I pump the pclk1 to mak speed
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<re_irc> < (@rhedgeco:matrix.org)> each bit is 1us and the gap bits are 1.5us
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<re_irc> < (@rhedgeco:matrix.org)> aaaaand it seems like if I set the hclk to its max speed and pclk back to 2MHz the problem is gone. weird but ill take it
<re_irc> < (@rhedgeco:matrix.org)> and I have to switch to BIDI mode
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<re_irc> < (@jamesmunns:beeper.com)> : Yeah, I suspect with a little bit of better pipelining, you could probably get rid of the gap
<re_irc> < (@grantm11235:matrix.org)> I think it is already pipelining. As soon as it sees TXE, it writes the data and starts trying to send the next word. It never actually waits for a word to finish being send on the line
<re_irc> < (@jamesmunns:beeper.com)> Ah, fair!
<re_irc> < (@grantm11235:matrix.org)> Oh wait. In non BIDI mode, it waits to recieve a word https://github.com/stm32-rs/stm32f4xx-hal/blob/master/src/spi/hal_02.rs#L114-L119
<re_irc> < (@grantm11235:matrix.org)> That kills the pipelining
<re_irc> < (@korken89:matrix.org)> : The const registration work and I'd say it's just as fine with 1:1 and 1:N IRQ:driver connections :)
<re_irc> < (@dirbaio:matrix.org)> 👀
<re_irc> < (@korken89:matrix.org)> * works
<re_irc> < (@korken89:matrix.org)> I think the syntax with arrow is quite nice as well
<re_irc> < (@korken89:matrix.org)> IRQ "connects to" list of drivers
<re_irc> < (@korken89:matrix.org)> At least it makes sense in my head 😅
<re_irc> < (@dirbaio:matrix.org)> 100% :D
<re_irc> < (@korken89:matrix.org)> Syntax can be bikeshed ofc
<re_irc> < (@dirbaio:matrix.org)> why make the token "owned"?
<re_irc> < (@korken89:matrix.org)> Owned?
<re_irc> < (@korken89:matrix.org)> Tokens impl copy
<re_irc> < (@dirbaio:matrix.org)> ah it's not owned anyway
<re_irc> < (@dirbaio:matrix.org)> * anymore
<re_irc> < (@korken89:matrix.org)> So you can sprinkle them around as much as you want :)
<re_irc> < (@dirbaio:matrix.org)> the "let xxx = register_interrupt!()" confused me
<re_irc> < (@korken89:matrix.org)> Ahh
<re_irc> < (@korken89:matrix.org)> I mean, one can make it work differently - all the magic is in const asserts and trait impls
<re_irc> < (@dirbaio:matrix.org)> yea
<re_irc> < (@korken89:matrix.org)> I quite like the "check 2 way"
<re_irc> < (@korken89:matrix.org)> So the macro checks the driver, and the driver checks the macro
<re_irc> < (@dirbaio:matrix.org)> the prototype I did was "register_interrupts!(Irqs, irq1: (func1, func2), irq2: (func3, func4));"
<re_irc> < (@dirbaio:matrix.org)> which declares a "struct Irqs;"
<re_irc> < (@dirbaio:matrix.org)> so you can do "Uart2::new(Irqs, ...)"
<re_irc> < (@dirbaio:matrix.org)> so it's clearer you can "conjure" an "Irqs" from anywhere...?
<re_irc> < (@dirbaio:matrix.org)> "let xxx = register_interrupt!()" looks like you have to "carry" it around
<re_irc> < (@korken89:matrix.org)> Ah, I guess that's fine as well
<re_irc> < (@dirbaio:matrix.org)> you could still "conjure" it from anywhere if you refer to it by the macro-generated name
<re_irc> < (@dirbaio:matrix.org)> +I guess
<re_irc> < (@korken89:matrix.org)> Yeah, but I don't think one will figure that our quite easily
<re_irc> < (@korken89:matrix.org)> * out
<re_irc> < (@korken89:matrix.org)> I can make it generate a struct though, no problem
<re_irc> < (@korken89:matrix.org)> Just need to come up with a syntax I can live with :(
<re_irc> < (@korken89:matrix.org)> * :)
<re_irc> < (@korken89:matrix.org)> Or just slap StructName, in the front as you did
<re_irc> < (@korken89:matrix.org)> I'll test it, see how it feels :)
<re_irc> < (@dirbaio:matrix.org)> (syntax for that snippet is still to-be-bikeshedded
<re_irc> < (@dirbaio:matrix.org)> have you thought about "N irqs in 1 token" too?
<re_irc> < (@korken89:matrix.org)> Yeah, I just want something that can get feedback at tomorrows' meeting :)
<re_irc> < (@korken89:matrix.org)> Hu
<re_irc> < (@korken89:matrix.org)> I guess that still works, but not in the same syntax
<re_irc> < (@korken89:matrix.org)> Just multiple macro calls
<re_irc> < (@dirbaio:matrix.org)> for cross-chip hals you kinda need it I think
<re_irc> < (@korken89:matrix.org)> It will not be stopped as it just expands with more impls
<re_irc> < (@korken89:matrix.org)> I'll test tomorrow :)
<re_irc> < (@korken89:matrix.org)> Time for bed here now though, thanks for the feedback!
<re_irc> < (@dirbaio:matrix.org)> otherwise you have to do this
<re_irc> #[cfg(stm32foo)]
<re_irc> #[cfg(stm32bar)]
<re_irc> fn new<T>(token: T) where T: InterruptToken<Func1> + InterruptToken<Func2> {..}
<re_irc> < (@dirbaio:matrix.org)> interrupt functions are sometimes separate sometimes not
<re_irc> < (@dirbaio:matrix.org)> across different chips in the same family even
<re_irc> < (@dirbaio:matrix.org)> or in different instances of the same peripheral (stm32 timers >_>)
<re_irc> < (@dirbaio:matrix.org)> if you can put N interrupts in the same token then the 1st case works for all chips
<re_irc> < (@dirbaio:matrix.org)> * signature
<re_irc> < (@korken89:matrix.org)> I pushed the fixed one
<re_irc> < (@korken89:matrix.org)> I need to try the multi chip one more
<re_irc> < (@korken89:matrix.org)> I'll give it a go tomorrow :)
<re_irc> < (@korken89:matrix.org)> But looking at it, it should be fine
<re_irc> < (@korken89:matrix.org)> coma separated list -> comma separated list
<re_irc> < (@korken89:matrix.org)> Instead of path -> comma separated list as I have now
<re_irc> < (@dirbaio:matrix.org)> mmm maybe more like "list of (irq -> function list)"
<re_irc> < (@korken89:matrix.org)> Could also be done :)
<re_irc> < (@korken89:matrix.org)> But now sleep, talk more later!
<re_irc> < (@korken89:matrix.org)> :D
<re_irc> < (@dirbaio:matrix.org)> and this is more of a philosophical one, but
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<re_irc> < (@dirbaio:matrix.org)> lol I forgot to write
<re_irc> < (@dirbaio:matrix.org)> stm32 needs this "irq function" stuff, but other chips don't
<re_irc> < (@dirbaio:matrix.org)> so adding support for it makes it harder to use for the chips that don't
<re_irc> < (@dirbaio:matrix.org)> but perhaps we should just take it
<re_irc> < (@firefrommoonlight:matrix.org)> Ralph: Depends on the details, but if the data is an unknown size, you might use Uart interrupts without DMA interrupt. Example: enable idle and char match interrupts (or rxne if you don't know start char) If char match flag is set, start the xfer and disable that interrupt. If idle is set, stop transfer, handle the data, And re enable char match
<re_irc> < (@firefrommoonlight:matrix.org)> You can only rely on TC if you know the message len, which some serial protocols don't have
<re_irc> < (@firefrommoonlight:matrix.org)> Depends on the details, but if the data is an unknown size, you might use Uart interrupts without DMA interrupt. Example: enable idle and char match interrupts (or rxne if you don't know start char) If char match flag is set, start the DMA xfer and disable that interrupt. If idle is set, stop transfer, handle the data, And re enable char match
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<re_irc> < (@grantm11235:matrix.org)> : Is the user expected to call "register_interrupt!" manually for each interrupt, or can this be done inside the HAL?
<re_irc> <Ralph> : thanks for the hint! the start char is "!" as in the linked protocol specification. but the length then depends on the second character. i think for now my setup (using DMA and line idle interrupt in combination) works fine - this isn't some large-scale production code, it's just a small tinkering project; as long as i reliably (enough) get my messages that's just fine
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