13:00 <re_irc> <henrikssn> What is the easiest way to convert a fugit Duration to an Instant (since epoch)?

13:01 <re_irc> <henrikssn> This is for unit testing, I want to e.g. have a Instant at "10.ms()"

13:02 <re_irc> <henrikssn> * "10.millis()"

13:03 <re_irc> <henrikssn> The best I've came up with so far is "Instant::<u32, 1, 1_000>::from_ticks(0) + 10.millis()" but it's super verbose and you can't infer the type arguments of "Instant" because it isn't supported for const generics

13:16 <re_irc> <jannic> "Instant::<u32, 1, 1_000>::from_ticks(10)" should do the same, but it's not much more readable to be honest. Perhaps define a "const EPOCH" for the instant, so you can write "EPOCH + 10.millis()"?

15:20 <re_irc> <henrikssn> jannic: That's OK but it only works for a concrete instant type

18:11 <re_irc> <dngrs (spookyvision@github)> so, scripting language on top of bare metal, what are my options? any? use case: pretty much exactly this (https://electromage.com/patterns)

18:24 <re_irc> <dngrs (spookyvision@github)> cliffle saves the day again (http://cliffle.com/blog/bare-metal-wasm/) I suppose

18:32 <re_irc> <dngrs (spookyvision@github)> plus "wasmi"

19:56 <re_irc> <yruama_lairba> Hi, i'm curious about rust embed development on multi-core target. Is there any documentation/blog post/what else talking about it ?

21:11 <re_irc> <newam> yruama_lairba: Depends in the core, for heterogeneous architectures it's generally as simple as making two binaries. For homogeneous it gets more difficult

21:13 <re_irc> <yruama_lairba> newam: in fact, i never done multi-core development in general, so i don't even know how it work in general

21:17 <re_irc> <yruama_lairba> for example, i don't know how to do synchronisation or pass data between core

21:20 <re_irc> <yruama_lairba> or i don't know what happen with interrupt

21:40 <re_irc> <newam> it depends on the core :P

21:40 <re_irc> A-series multicore has a GIC (usually) with an interrupt distributor per-core, but M-series cores operate independently and you're relying on vendor peripherals for synchronization

21:41 <re_irc> <newam> and that's just ARM, xtensa/RISC cores have a lot of flexibility, multi-core can be very different depending on the SoC with those

21:42 <re_irc> <newam> * xtensa/RISCV

21:51 <re_irc> <yruama_lairba> wow, i didn't know it was so dependent of the chip. I may target rpi pico in future, but don't have any plan yet. i just wanted to have a genral overview of multi-core development, for example what crate i can use or not and if there crates to makes easier such development

21:53 <re_irc> <newam> The rpi pico is probably the easiest multi-core micro-controller class chip to start with, since the cores are mostly symmetric.

21:53 <re_irc> Don't know of any crates that make multi-core on it easy though, but I'm sure someone has done it since it's the only chip in stock in 2022 🤣

21:56 <re_irc> <dirbaio> rp2040-hal has a function to spawn code into the 2nd core https://docs.rs/rp2040-hal/latest/rp2040_hal/multicore/struct.Core.html#method.spawn

21:57 <re_irc> <yruama_lairba> i found by chance an old blog post talking about multi-core support in rtic ? is it true ? i never found anything about multicore in rtic doc

21:58 <re_irc> <dirbaio> it uses plain old Send+Sync to model safety, note how it requires the spawned function to be Send

21:58 <re_irc> <dirbaio> it treats the two cores like two threads

21:59 <re_irc> <dirbaio> rtic doesn't support multicore, it used to in the past but it was removed https://github.com/rtic-rs/cortex-m-rtic/pull/355

22:02 <re_irc> <yruama_lairba> thanks for information. i followed discussion and it seems rtic never supported multicore in stable rust