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<re_irc> <@korken89:matrix.org> pinealservo:matrix.org: Yeah, the AUTOSAR OS is also an SRP based kernel, the same as we have designed RTIC around :)
<re_irc> <@pinealservo:matrix.org> I went down a rabbit hole of reading AUTOSAR specification documents back in the day to try to understand some of its network-related specifications stuff. That was not a lot of fun.
<re_irc> <@korken89:matrix.org> Yeah, it's quite tedious. Especially after getting used to Rust docs xD
<re_irc> <@korken89:matrix.org> Btw if you want to discuss RTIC feel free to join us at #rtic:matrix.org :D
<re_irc> <@pinealservo:matrix.org> I've been listening there for a while, and I've played around with a little bare-bones blinky project with RTIC on a blue pill.
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<re_irc> <@burrbull:matrix.org> adamgreig, therealprof https://github.com/rust-embedded/svd/pull/154
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<re_irc> <@newam:matrix.org> Unrelated topic, but I know there are some FPGA folks in here.
<re_irc> <@newam:matrix.org> Anyone got recommendations for a large-sized FPGA development board that works with an open source toolchains?
<re_irc> <@adamgreig:matrix.org> for larger fpga with a decent open source toolchain you probably want to look at lattice ecp5, for a dev board you could look at lattice ecp5 versa, or ulx3s for a cheaper open-source dev board
<re_irc> <@adamgreig:matrix.org> lattice have a list of ecp5 dev boards including a bunch of open source ones: https://www.latticesemi.com/solutionsearch?qprod=122b6ed41fa54963b341bd67866f7078&qiptype=982db688d64345bbb3af29e62fee1dc3
<re_irc> <@adamgreig:matrix.org> kinda depends a lot on what you mean by "large-sized" though
<re_irc> <@newam:matrix.org> adamgreig: Well I got one of these and I run into the space limits too frequently: https://www.seeedstudio.com/Sipeed-Tang-Nano-FPGA-board-powered-by-GW1N-1-FPGA-p-4304.html
<re_irc> <@newam:matrix.org> I don't have any real application, I just want to play around without hitting hardware limits as frequently.
<re_irc> <@adamgreig:matrix.org> oh, yea, those are very tiny
<re_irc> <@adamgreig:matrix.org> those are about 1k LUTs, the lattice ice40 (simpler and smaller with open-source toolchain) are 5k or 8k typically, and the ecp5 are 25, 45, or 85k LUTs
<re_irc> <@adamgreig:matrix.org> the ice40up5k is 5k luts and very popular because it's in a neat qfn48 package and has 8 hardware multipliers and a large single port ram as well as normal block RAMs, but the core logic is quite slow (though still faster than the gw1n I believe, you might expect 25-75MHz)
<re_irc> <@adamgreig:matrix.org> the ice40hx8k is 8k LUTs and more like 100-150MHz, but no hardware multipliers, and qfp/bga packages
<re_irc> <@adamgreig:matrix.org> the ecp5 is 25/45/85k LUTs, lots of hardware DSP/multipliers, lots of RAM, maybe 200-400MHz
<re_irc> <@adamgreig:matrix.org> (clock speeds all extremely rough as it totally depends on your design)
<re_irc> <@adamgreig:matrix.org> so if you just want something a bit bigger to play with, maybe something like https://1bitsquared.com/collections/fpga/products/icebreaker with an ice40up5k would be fun and 5x bigger than what you have
<re_irc> <@adamgreig:matrix.org> ecp5 tends to be big enough to also often have external ram, like https://1bitsquared.com/collections/fpga/products/orangecrab with 128MB DDR3
<re_irc> <@adamgreig:matrix.org> _loads_ of project examples for icebreaker and similar up5k boards
<re_irc> <@newam:matrix.org> That helps a ton, thanks :D
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<re_irc> <@adamgreig:matrix.org> burrbull: does svd2rust only make an array out of a cluster if no padding is needed?
<re_irc> <@adamgreig:matrix.org> ah I see, it's https://github.com/rust-embedded/svd2rust/pull/534
<re_irc> <@adamgreig:matrix.org> boo, that would be really nice for the stm32h7 dfsdm i'm just wrapping up, lol
<re_irc> <@adamgreig:matrix.org> don't get why it can't just add some padding to the cluster struct though
<re_irc> <@adamgreig:matrix.org> ah, the reason why is in https://github.com/rust-embedded/svd2rust/pull/531, cool