sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<vagrantc> .23
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<obrut> anyone knows which ehternet controller p550 has ? realtek ? something else ?
<obrut> also, I would really like to know result of the "povray -benchmark" on p550 if someone can run :) I suppose it exists in ubuntu repos...
<drmpeg> It uses a Synopsys DesignWare Ethernet controller on the SoC.
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<obrut> drmpeg: thanx
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<wigyori> hi - does someone know how to build an fsbl image for the sg2002 with a mainline toolchain i.e. gcc13 ?
<wigyori> gcc13 drops an "Error: x ISA extension `xthead' must be set with the versions" - there is an icache.iall and sync.i call in the cpu_helper.c
<wigyori> for the cv1800 (i.e. the milkv duo) there is a prebuilt bl2, so i can build a mainline u-boot, but couldn't find such for the sg2002
<bjdooks> that sounds more like a binutils issue, not a gcc one
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<palmer> wigyori: ya, and you're probably missing something like "xtheadvector1p0" in the "-march" string. I think Charlie's latest patches should work, but if you're using vendor trees then you'll probably have to make sure how it's enabling the extensions matches what the toolchain wants
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<bjdooks> ok, updated https://gitlab.com/CodethinkLabs/riscv_bigendian with new readme about how things are going
<bjdooks> looks like some issue with floating point i need to chase down
<jrtc27> big endian, oh no
<geertu> the only true endianness ;-)
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<wigyori> palmer / bjdooks: a change to -march=rv64imafdcvxtheadcmo1p0_xtheadsync1p0, and an s/sync.i/th.sync.i/ s/icache.iall/th.icache.iall/ seems to have done the trick - thanks. Now it's the "unknown CSR `mhcr'", i'll try to find something similar for that
<palmer> If you know the CSR number you can just use that instead of the name, that's what we usually do in Linux to avoid getting coupled to assembler versions
<jrtc27> 0x7C1
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<geist> huh, they're not here anymore, but why would ASID support negatively impact perf on the p550? is there hardware errata?
<geist> or is that a function of linux + riscv + that hardware?
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<ganboing> No ASID support (or 0-bit) will force much more TLB flushes especially with frequent context (process) switches
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<wigyori> palmer / jrtc27: works^Wcompiles :) a couple other CSRs had to be hardcoded as well, but with that the sg200x bl2 compiles - thanks
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<geist> oh oh i misread it
<geist> i read the original statement as 'asid support will'... vs '*no* asid support'
<geist> yeah that makes sense
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