cfbolz changed the topic of #pypy to: #pypy PyPy, the flexible snake https://pypy.org | IRC logs: https://quodlibet.duckdns.org/irc/pypy/latest.log.html#irc-end and https://libera.irclog.whitequark.org/pypy | the pypy angle is to shrug and copy the implementation of CPython as closely as possible, and staying out of design decisions
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<vext01> Hey, I'm studying the pypy codegen backends. It looks like a forward traversal of the IR ops, with register allocation interleaved, is that correct?
<vext01> you don't do reverse register allocation?
<vext01> found this which confirms this I think: https://rpython.readthedocs.io/en/latest/jit/backend.html#assembly
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<cfbolz> vext01: we do one reverse pass for lifetime analysis
<cfbolz> but indeed no backwards register allocation
<vext01> cfbolz: thanks
<vext01> also, hello :)
<cfbolz> hey :-)
<cfbolz> vext01: honestly our backends aren't very good
<vext01> good enough, by the look of it
<vext01> we are weighing up adding "reverse assembly" support to dynasm-rs so that we can visit our IR ops in reverse and do better regalloc
<vext01> i noticed some kind of register allocation "hinting" system
<cfbolz> yeah, a little bit. but not very smart, all in all
<vext01> does this just note fixed registers required in the future for stuff like ABI constraints?
<vext01> "try and store it here if you can, because we will need it there later"?
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<cfbolz> vext01: yeah, exactly
<cfbolz> also stuff like 'try not to put these to variables in the same registers because their lifetimes overlap'
<vext01> thanks, this is pure gold in terms of saving us some implementation effort!
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