<gamiee>
Hi! I am working on TCL scripts for MCU with RISC-V core SiFive E24. I would like to ask several questions, as I couldn't find answer for them.
<gamiee>
When reseting the board through "reset" (reset_config is in default state), what is expected behavior of the chip? It should reset all peripherals, and also CPU (so the PC is on beginning of BootROM)?
<PaulFertser>
Hi
<PaulFertser>
gamiee: "reset" is "reset run" and it should be as close to normal power on reset (and letting the target run after that) as possible.
<PaulFertser>
There's also "reset halt" which means that the target must be halted as early as possible, before the first instruction of reset vector or some such.
<PaulFertser>
"reset init" is just "reset halt" followed by execution of Tcl target-specific init handler, used to prepare the target for flashing with OpenOCD.
<PaulFertser>
reset_config is to tell OpenOCD what reset lines are connected and how the target treats them.
<PaulFertser>
gamiee: so to answer your question specifically, yes, it should reset all peripherals and CPU and let it start executing from beginning of BootROM.
slobodan has joined #openocd
<gamiee>
PaulFertser : Hello and thank you for your fast answer. Since you know the chip, it is about bl702. I am writing target tcl for it and I would love to upstream them when ready.
<gamiee>
Also, this is bad information for me, as reset basically does nothing, since I don't see any change after reset. CPU stays on same PC as it was before, and thus I can expect that also peripherals are in default state.
<gamiee>
It looks like only TAP is reset when issues, everything is kept as is. Sadly, I really don't know how this behaves on other RISC-V chips. I checked the few ones which are upstreamed, (probably) they were using hw reset pin.
<gamiee>
gd32vf103.cfg is only reference, which also have custom reset sequence, as "ndmreset" doesn't work on it. I guess bl702 is also the case?
nerozero has quit [Ping timeout: 256 seconds]
slobodan_ has joined #openocd
slobodan has quit [Ping timeout: 264 seconds]
<PaulFertser>
gamiee: on modern Cortex-M there's a generic standard SYSRESETEQ bit to force proper restart. On other ARM cores it used to require either physical reset line or when it's not connected OpenOCD could run a script to trigger reset via watchdog.
<PaulFertser>
That gd32vf103.cfg looks like a reasonably good example of what to do with a silly chip.
<gamiee>
PaulFertser : yeah, it is very good example. I also inspired from some Espressif not upstreamed work.
<gamiee>
I found function which does reset of the chip, at least in level that it "by nature" jumps into bootrom and starts from scratch (but at least, GPIO peripheral is not reset). Although, for some reason, the OpenOCD does not halt the chip, it just resumes.
<gamiee>
Shouldn't be OpenOCD trying to halt the CPU right away? Or my code should take care of it?
<gamiee>
I tried both reset-assert and reset-assert-post (that's what Espressif uses)
<PaulFertser>
gamiee: reset run shouldn't try to halt the chip
<gamiee>
reset run works OK, but reset halt does not.
<PaulFertser>
That's a bad reset if peripherals are not reset.
<gamiee>
not sure what all is reset, there is chance that only GLB (GPIO) is not reset, need to play with it. But this is good start for me.
<gamiee>
The problem with this is as follows:
<gamiee>
when I use dmi_writes (for halt req), the chip is halted, but for some reason, PC gets into some weird address, and hardfault irq (from bootrom) is thrown. (not sure if the irq table is kept or bootrom actually executes and something went wrong)
<gamiee>
when I don't use dmi_writes, chip restarts successfully, but it does not halt (when reset halt is issued)
<PaulFertser>
Unfortunately I have zero RISCV experience
<gamiee>
no worries, this is all new for me too
<gamiee>
I think I made it, seems to work.
<gamiee>
I put reset "code" into reset-assert-pre, then default assert_reset is executed, and it seems to work well, the CPU is halted in initials of BootROM.
<gamiee>
thanks for help PaulFertser :)
<PaulFertser>
gamiee: sorry not much of help but hope clarifications about semantics encouraged :)
gpol has joined #openocd
zjason`` has quit [Read error: Connection reset by peer]