15:57 <mark_feathers> I'm trying to add support for a Renesas EK-RA4M2. If I "reset halt" it comes back with "TARGET: ra4m2.cpu - Not halted". I found out if I run it < 800khz, then I can reset halt as I expected. The part is supposed to allow SWD/JTAG to 25 MHz.

15:57 <mark_feathers> Anyone have any ideas why the speed might be so limited? This EVK has a built in jlink that is limited to 2mhz, but I'm hoping to use it on my own board with jtag at 10mhz.

16:05 <Hawk777> On some processors, there is a relationship between the maximum workable JTAG and/or SWD speed and the speed of the CPU clock. If the CPU clock is running slowly, that may force the JTAG/SWD clock to also be slow. In my experience OpenOCD config files for such processors generally set up a PLL to boost the CPU clock rate in a “reset init” handler so that the JTAG/SWD speed can then be boosted during Flash programming.

16:26 <mark_feathers> They dont seem to document that relationship, or I haven't found it yet, but that makes sense. I'll try to bump up the clocks and see if I can talk faster. Thanks!

16:27 <karlp> what is the reset clock?

16:35 <mark_feathers> It looks like the ARM clock might be 2mhz out of reset

16:35 <mark_feathers> I didn't realize that before, certainly not talking 10MHz to that

16:35 <karlp> yup :)