14:45 <Guest72> I am having issues connecting to a processor when it is in low power mode. I have tried to connect under reset and have had no success. I have been able to do it by setting C_DEBUGEN in DCB_DHCSR but I can't do it until the target is examined but the target can't be examined until I do this. Am I missing something here as far as doing this another

14:45 <Guest72> way? I am thinking of adding an examine-first event for anything that needs to happen as soon as the target is examined.

14:52 <PaulFertser> Guest72: hi

14:52 <PaulFertser> Guest72: what chip exactly is that?

14:53 <Guest72> It's an M4 on the MAX32655

14:54 <PaulFertser> Guest72: hm, and does the vendor datasheet give any hints? If it's one of those broken implementations when SWD doesn't work with RESET asserted then there must be some other documented way to talk to it.

14:54 <PaulFertser> Also there often is some /additional/ non standard configuration bit to allow debugging in low power moodes.

14:59 <Guest72> Not that I have seen. The only thing I have seen from searching is to add some delay before going to low power mode to allow for the debugger to break in. It could be that I am failing to figure out the right sequence or that SWD indeed doesn't work with RESET asserted.

15:00 <Guest72> What I found was in a support issue that I ran across.

15:12 <PaulFertser> Guest72: it should just work with -c "reset_config srst_only connect_assert_srst"

15:12 <PaulFertser> That's the only setting needed with a proper target.

15:15 <Guest72> I will double check but I believe I did try that. I have tried so many things though that I want to go back and make sure. Failing that, it doesn't sound like you are very keen on my idea to add an examine-first event...is that accurate?

15:17 <PaulFertser> Guest72: I do not see how you can do anything at all if SWD doesn't work in the first place at all anyhow.

15:22 <Guest72> If I did what I was thinking I would not be doing it while RESET is asserted so SWD does work in that case. It would just allow me to write to a register as soon as target is examined rather than reading the cpuid which is failing.

15:23 <Guest72> Then I would read cpuid and continue right after I enable the debug

15:28 <PaulFertser> Guest72: if it allows that then yes, an event handler might do the job.

15:28 <PaulFertser> I thought you had no SWD access at all in with RESET asserted.

15:30 <Guest72> Right, but RESET is not asserted when in the cortex_m_examine function.

15:33 <PaulFertser> Guest72: it is if you use connect_assert_srst flag.

15:36 <Guest72> Ohh. Sorry, gotcha. In this case I would not be using that. I will try the standard way first which is what you stated as far as using -c "reset_config srst_only connect_assert_srst" to verify I had already tried that and it failed. If that doesn't work then I would only use -c "reset_config srst_only"

15:39 <Guest72> ...and try adding a new examine-first event

15:42 <wmat> In case anyone here is interested in upstreaming RISC-V support, there's an RFP open for the project: https://wiki.riseproject.dev/display/HOME/Project+RP007+RISC-V+OpenOCD+Upstreaming?utm_content=287151964&utm_medium=social&utm_source=linkedin&hss_channel=lcp-97448757