<rue_mohr>
pleaaaaaase, I dont want to just give up now
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<PaulFertser>
rue_mohr: svf just plays back the SVF file, it's very low level JTAG sequence of commands.
<rue_mohr>
it looks like the altera fpga might stay in reset mode
<rue_mohr>
the docs dont say if configuring it via jtag will bump it out or not
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<PaulFertser>
rue_mohr: does the svf play back without errors?
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<Guest15>
hello there! I want to make a new flash driver for my specific chip. I am wondering if there is any tutorial about it since I didn't find out so much about how to write one.
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<PaulFertser>
Guest15: hi
<PaulFertser>
Guest15: no tutorial but you can do "git log src/flash/nor" and see one of the drivers that was added recently and use that for inspiration.
<Guest15>
cool thx
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<wtywtykk>
rue_mohr: using a BGA chip with wires is not a good idea....I think it's unlikely to work without proper decoupling.
<wtywtykk>
Also why use openocd? Altera has their own tools to program the FPGA
<karlp>
you joined specifically to say "don't use the tools this channel is for" ?
<PaulFertser>
:D
<wtywtykk>
No offense, I think starting from the official tool should better isolate the problem.
<PaulFertser>
There's also the question about how that SVF file was generated.
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<rue_mohr>
wtywtykk, at 460Hz?
<PaulFertser>
rue_mohr: how did you generate the svf file? Were there any errors when you played it back?
<rue_mohr>
there were no errors, I used.. command lines to generate it from a verilog
<rue_mohr>
LD_LIBRARY_PATH=/files_loc/altera/13.0sp1/quartus/linux64:$LD_LIBRARY_PATH /files_loc/altera/13.0sp1/quartus/linux64/quartus_sh --prepare main
<rue_mohr>
LD_LIBRARY_PATH=/files_loc/altera/13.0sp1/quartus/linux64:$LD_LIBRARY_PATH /files_loc/altera/13.0sp1/quartus/linux64/quartus_map main
<rue_mohr>
LD_LIBRARY_PATH=/files_loc/altera/13.0sp1/quartus/linux64:$LD_LIBRARY_PATH /files_loc/altera/13.0sp1/quartus/linux64/quartus_fit main
<rue_mohr>
LD_LIBRARY_PATH=/files_loc/altera/13.0sp1/quartus/linux64:$LD_LIBRARY_PATH /files_loc/altera/13.0sp1/quartus/linux64/quartus_asm main
<PaulFertser>
rue_mohr: if SVF play back showed no errors it means the vendor software generated it in a wrong (for your purposes) way.
<rue_mohr>
?
<rue_mohr>
what error should I see?
<PaulFertser>
rue_mohr: you used quartus to generate SVF. It just tells what JTAG operations it would do if it had a hardware adapter. Then you let OpenOCD play it back. If OpenOCD doesn't complain then it means everything went according to (quartus) plan.
<rue_mohr>
you mean because it doesn't work?
<rue_mohr>
right now, I have a verilog file that should put one IO line high and the other low, they are connected to leds, neither of them are lighting up
<PaulFertser>
rue_mohr: SVF files have values to compare. If the chip was returning data that quartus didn't expect then you'd see an OpenOCD error.
<rue_mohr>
but I dont know if, on the cyclone II, I need to raise nCONFIG
<rue_mohr>
if I were using serial config, I can see, yes, but its not clear if thats needed when configuring via jtag
<wtywtykk>
It's possible a large amount of gates toggle simultaneously during configuration, and create a current spike.
<wtywtykk>
Did you add a pull-up resistor to nConfig?
<rue_mohr>
:( no
<rue_mohr>
I think its most likley to be a problem than not having connected MSEL0 & 1
<rue_mohr>
I can plausibly see if flipping back into config mode
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<wtywtykk>
Try add a pull-up resistor, seems the pin doesn't have internal pullup
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<rue_mohr>
yea, thats NOT easy
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