<cr1901>
Okay, openfpgaloader just suddenly refuses to program my icebreaker properly (iceprog works fine). It looks like OFL is leaving the SPI flash clock running.
<cr1901>
What recourse do I have (--verbose-level 2 does not print anything special)
<cr1901>
bisected to ecb22b2eeb2a... Reverting that commit fixes OFL for me. Tested on both Windows and armv7 32-bit Linux
<cr1901>
According to the Logic Analyzer, the clk to the SPI flash continues to run after OFL exits, which means the FPGA sees garbage when it tries to drive the bus to load its bitstream