trabucayre changed the topic of #openFPGALoader to: Universal utility for programming FPGA / Github: https://github.com/trabucayre/openFPGALoader/ Logs: https://libera.irclog.whitequark.org/openFPGALoader
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<Niklas> Hi everyone! I have a question around programming an Efinix Trion T8. I'm designing a board using that FPGA and I'm trying to determine if I need to connect CRESET_N if I tie SS_N to ground.
<Niklas> I'm looking at the source code in Efinix::programJTAG() and the first thing that it does is to reset the FPGA and set SS_N low (asserted) when CRESET_N is deasserted so that the FPGA ends up in passive mode.
<Niklas> So I'm wondering if I would tie SS_N to ground, would that be enough for JTAG programming to work, or does the fpga still need to be reset before programming starts?
<trabucayre> Niklas: it's to have access to the SPI flash
<trabucayre> I have to reread. Too many FPGAs in my mind :)
<Niklas> :)
<trabucayre> there is also a work around for xyloni (with oe)
<Niklas> Yes
<trabucayre> why my code is not more documented :(
<Niklas> Lol, it's the same for me, always
<trabucayre> ok for spi trion must be in reset mode to allows access to the flash (it's exactly the same situation for ice40)
<trabucayre> this why rstn is low
<Niklas> On page 6 of this document, https://www.efinixinc.com/docs/an038-programming-with-mcu-and-jtag-v1.0.pdf, it says how to enable JTAG programming for Trion T35 (for example), and on page 7 is how to enable JTAG programming for T8
<trabucayre> and for jtag cs must be low during reset to allows access to the jtag (I'm not sure but I think to a trion's bug)
<Niklas> The difference is that for T8 it says: "2. Pulse CRESET_N (1 to 0 to 1) at the beginning of configuration. The FPGA(s) go into
<Niklas> passive mode. You can probe the FPGA's SCK pin to confirm that it is tri-stated."
<Niklas> I'm too am guessing it's a workaround for a bug
<trabucayre> I have to check into efinix's code
<Niklas> I read this comment, related to those Trion chips that don't require to put the device in passive mode first: https://github.com/trabucayre/openFPGALoader/pull/218
<Niklas> For for T35 (for example) it is enough to use normal JTAG pins only, but not on T8. T8 needs to be put in passive mode first (it seems).
<trabucayre> yep
<Niklas> I'm thinking that if I could put the T8 in passive mode manually (not using pins that are connected to the computer used to do the programming) then maybe it then works to use JTAG pins only.
<Niklas> Maybe I just have to try and see if it works. The whole procedure certainly feels like a workaround for bug.
<trabucayre> This sequence it's required due to a bug
<Niklas> Do you have this on some inside knowledge?:)  I also think it's highly likely, but perhaps Efinix have stated so somewhere.
<trabucayre> from the programmer:
<trabucayre> # if this is T8/T4, it has the error hw state for JTAG programming.
<trabucayre> # We will attempt to account for it here, by controlling GPIO0/1
<trabucayre> # (ADBUS4, ADBUS5)
<trabucayre> I haven't datasheet at hand
<Niklas> What code is that from?
<trabucayre> outch:
<trabucayre> commit 70fb5c84398181e08f56eaca4d9b8297ac61ec99
<trabucayre> Date: Sat Oct 31 08:46:53 2020 +0100
<trabucayre> Author: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
<trabucayre> add efinix support
<trabucayre> efinix/efinity/2022.2/pgm/bin/efx_pgm/ftdi_program.py:l.1568
<Niklas> Ah, excellent. I hadn't seen that code before, I will read it.
<trabucayre> But this file isn't my primary source of information... Unfortunately can't remember where I found that
<Niklas> This is super helpful still. I think I have enough circumstantial evidence now so that I will go ahead and build the board based on these assumptions (knowing that they might still end up being false and I will have to rework it).
<trabucayre> I have to find this one and add a note...
<trabucayre> Maybe this issue is fixed with recent release but this WA seems clear
<trabucayre> (and required)
<Niklas> Yes
<trabucayre> It's not true for all titanium and trion but since an SPI interface is required to write flash I assume this WA is not a big issue
<trabucayre> it's just boring (to my side) because SPI interface must be deduce for JTAG mode
<Niklas> The reason why I want to get the JTAG programming mode working is so that I can write the configuration to SRAM directly instead of writing to Flash for every iteration, during development
<trabucayre> make sense :)
<trabucayre> (and I do the same thing)
<Niklas> Btw, do you use Discord? I don't have any convenient way to stay online on IRC, but this channel seems very interesting to me.
<trabucayre> there is no bridge...
<Niklas> I think Claude Schwarz set up a bridge between discord and IRC in the beginning of the Pistorm project. Not sure how that works exactly though.
<Niklas> If you ever chose to set up a Discord server I will join immediately :D
<Niklas> In any case, thanks for your time and expertise! I appreciate it. If I get this board working I will send you a tweet so you can see it (it's a project related to Amiga).
<trabucayre> many IRC have a bridge. It make sense to create one for this channel... But I have no idea on how to do that
<Niklas> I think you have to create a Discord server first, and then you can bridge them (somehow, not sure how).
<trabucayre> thanks! And always happy when I can help!
<Niklas> :)  See you
<trabucayre> See you.
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