<coco3431>
I'm trying to load my bitstream onto a Sipeed Tang Primer 20K (Lite) using the included USB Sipeed JTAG board, but keep getting stuck at ~75%. I'm able to detect the FPGA properly so I believe that would mean I have it all hooked correctly. Verbose shows its getting stuck in Gowin::pollFlag as its always getting 0xA1 back from readStatusReg(),
<coco3431>
never getting the Done Final bit to be set. I went through the Gowin JTAG programing guide but am not seeing anything incorrect about the flashing sequence at first glance. Also tried setting the freq lower but it seems to be resetting it to 2.5MHz before starting the Erase/Flash sequence. Planning on borrowing a Windows PC later today to test with
<coco3431>
Sipeed's programing software just to rule out any issues with HW if I can't get figure it out
<trabucayre>
the good (and bad) thing is the one whos opened the issue is now able to program this board. I suspect some glitches during load: can you check cable connections?
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<coco3431>
I've checked my connections a few times and I'm pretty they should be okay. Using Sipeed's Windows software I was able to get it to load the bitstream without errors as long as I didn't try to verify it. It would always fail the verify and the status would always come back with the CRC Error bit set. Gonna have to get out my scope anyway to check
<coco3431>
if my design is actually loaded or not so might as well double check the jtag lines. Thanks for all your work on this program :)
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<trabucayre>
If security bit is set you can't verify
<trabucayre>
but If status register shows a CRC error it's weird
<trabucayre>
Have you retried openFPGALoader after your test using vendor programmer?
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<coco3431>
Yep will verify without issue with the vendor software after undoing the security bit, suppose that makes a lot of sense and was some user error on my part. I was able to follow up with 4-5 loads in a row using openFPGALoader without locking up. But upon trying the litex-boards example and it put me back into that same state, so I think I need to
<coco3431>
look into how the gowin project is setup and built in litex to figure that out. Weirdly even with a successful load I haven't been able to verify a design is actually running yet, pins just seem to stay high.
<trabucayre>
coco3431: it's weird. Most of works I have done since receive my 20k was with litex without any issue
<trabucayre>
coco3431: gowin has a good hard but docs are naught :-(
<trabucayre>
docs about programming are not complete, I suspect some lack into openFPGALoader in some specific cases :(
<trabucayre>
Ok it's not gowin's specific: it's true for intel/altera too. I spent much time with max10 (and unable to find an arrow deca)
<trabucayre>
but for MSPI you have a figure and an FSM and for some primitives you have a picture: no parameter details, nor signals size :)
<coco3431>
I'll have to order another board to rule out a hardware issue. Was waiting until Sipeed released their board with the additional peripherals but who knows how much longer I'd have to wait
<coco3431>
Hopefully someday the vendors will work towards supporting more opensource tooling. Still have nightmares about getting specific versions of Quartus2 setup for old Cyclone chips haha
<trabucayre>
the dock standard will (theoretically) released mid-october
<trabucayre>
don't joke with old cyclone: Cyclone II are used at university... :(
<trabucayre>
There is a (french) article on how to use quartus 13 with a modern distro (and docker)
<coco3431>
Last I saw on their twitter they said around September 15th is why I was waiting, but stuff happens will just have to wait
<coco3431>
That's exactly why I was having to install it! Good ole Altera DE2 kits at university. I did see the docker stuff more recently, but haven't used any Altera chips since I graduated
<trabucayre>
at university where, sometime, I lecture it uses this board and way of coding is like done 15 years ago :)
<trabucayre>
Students are lost when reading code I provides :)