<d1b2>
<mattvenn> I tried passing it in to the instantiation of Blinky, but that doesn't work. I couldn't find much in the way of reference to what options the simulator has
<d1b2>
<mattvenn> this works for simulating and programming
<d1b2>
<mattvenn> look OK? I want to check I'm not missing some obvious language feature that would make this easier
<whitequark>
basically ok
<d1b2>
<mattvenn> I'm going to make a video about this, so if you prefer something different, please tell me
<whitequark>
I think this is reasonable, but let me DM you about something
<whitequark>
oh, wait, Discord, I'll message you on Slack theb
<d1b2>
<mattvenn> I want to write a test for my nMigen module and run it against the OpenRAM memory model (which is in Verilog). I looked about for how to include Verilog modules and found this: https://github.com/m-labs/nmigen/issues/1
<d1b2>
<mattvenn> Is there anything else out there? For example how to run a test with that included verilog?
<d1b2>
<mattvenn> example also doesn't work as lower seems to be deprecated
<d1b2>
<dragonmux> You could use the cxxrtl backend to create a testbed and then write your tests that way
<d1b2>
<dragonmux> That'd use the verilog sources properly for the sim
<d1b2>
<mattvenn> I was wondering if it's possible to do this all within the simulator that comes with nMigen
<d1b2>
<mattvenn> but maybe not.
<d1b2>
<dragonmux> Pysim can't see the verilog source
<d1b2>
<mattvenn> In which case I'll probably switch to cocotb and dump the verilog
<whitequark>
the upcoming cxxsim simulator will be able to cosimulate with Verilog
<whitequark>
but it's not ready yet
<whitequark>
also, you're referring to the wrong GitHub repo above
<d1b2>
<mattvenn> oops
emeb has joined #nmigen
_whitenotifier-e has joined #nmigen
<_whitenotifier-e>
[YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JMuOe