<minute>
there's probably still no known way to correctly calculate mipi dsi phy timings on amlogic a311d right?
<minute>
imx93 and rk3568 both also have dw mipi dsi and they have struct hstt hstt_table[]
<minute>
that are slightly different but yet similar. but the numbers for a311d are totally different
<minute>
(the few that we have)
<minute>
i've spent a few days and i just can't get a new display to work on that chip that i got to work with both imx8mp an rk3588... it's really weird. it's almost ok but the display is horizontally wrapped
<minute>
like, in the middle or at 2/3rds approximately
<minute>
futzing with the dw_mipi_dsi_phy_get_timing changes it a bit
<narmstrong>
yeah it looks like some horizontal timing is added by the encl timing generator, I never found exactly how
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<minute>
narmstrong: hmm any register i could play with?
<minute>
narmstrong: do you mean in general the stuff in meson_venc_mipi_dsi_mode_set ?
<narmstrong>
Yeah, I checked the calculations multiple times and I didn’t find anything obvious
<minute>
narmstrong: but what kind of problem did you encounter? horizontal wrapping also?
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<narmstrong>
Sort of, it was long time ago
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<minute>
i think it's more likely to do with the lp2hs etc stuff, because switching between the two "presets" changes the horizontal offset
<narmstrong>
I never understood those numbers, they are probably related to the lp frequency
<minute>
also it looks like it's IP version < 131 so the range is only max 255
<minute>
i seem to be able to get only those two different (~1/2 wrapped and ~1/3 wrapped) scenarios... so i'm likely to give up on this today and we should probably discontinue this model
<minute>
interestingly lp2hs numbers between 15-50 don't seem to work at all, but extreme numbers like 1 or 255 do