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<cyrozap>
ndufresne: Regarding the MediaTek video encoder/decoder RE discussion we had a couple days ago, if you're interested in reverse engineering that MediaTek encoder/decoder hardware, the MT8183's VPU firmware is actually run on an ARMv7-M core, not an MD32 (MediaTek custom ISA) core. In fact, IIRC, the MT8183 actually completely lacks an MD32 core, so it's not a suitable target for MD32 ISA RE. But
<cyrozap>
because the MT8183 VPU firmware is being run on an ARM core, there's no need to do any ISA RE in order to disassemble the binary (which is a standard ELF file) and understand the video codec hardware itself, making it an ideal target if you're more interested in doing that.
<cyrozap>
That firmware does more stuff than just manage the video codec, why it's called "SCP" in the MT8173 and not "VPU" like it was in the MT8173, but that should still contain some code for talking with the host and the video codec.
<cyrozap>
Oops, typo: "...why it's called "SCP" in the *MT8183* and not "VPU" like it was in the MT8173..."
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<cyrozap>
In case anyone cares about the MediaTek MT8183 SCP stuff, it seems the firmware is just a proprietary build of Chromium OS's EC (https://chromium.googlesource.com/chromiumos/platform/ec/), and you can probably get most of the functions auto-named by building the "kukui_scp" board target from the v2.0.0 tag (or maybe one of the *-kukui-* tags?), importing that ELF into Ghidra/IDA, generating
<cyrozap>
signatures for all the functions, and then using those signatures with the linux-firmware `scp.img`.
<cyrozap>
Anyways, I don't want to clutter an Amlogic channel with MediaTek RE talk, so if anyone wants to discuss this further, you can find me in #postmarketos-lowlevel on OFTC (#lowlevel:postmarketos.org on Matrix).
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<narmstrong>
cyrozap: the MT8183 lacks any dedicated cpu to run the vdec/venc/mdp firmware
<narmstrong>
cyrozap: on their bsp, they actually run this from user-space
<narmstrong>
cyrozap: but for chromeOS MTK developed a firmware in the SCP m4 coproc, that wasn't designed for that
<narmstrong>
this is why is does only stateless, the user-space firmware does statefull
<narmstrong>
but the underlying HW is quite complex and well hidden
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<cyrozap>
narmstrong: Yeah, that's what I gathered looking at the kernel code and chromiumos-ec sources, but thank you for the confirming that.
<cyrozap>
"this is why is does only stateless, the user-space firmware does statefull" <- I'm having trouble understaning this. Do you mean that the hardware is stateless, and the firmware and bsp code make it stateful and hide hardware details?
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<narmstrong>
yep
<narmstrong>
the HW is just a bunch of accelerators (like in any SoCs)
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