00:07
fibmod has quit [Ping timeout: 252 seconds]
00:12
klausvalka has joined #glasgow
00:32
fibmod has joined #glasgow
01:14
fibmod has quit [Ping timeout: 260 seconds]
01:40
fibmod has joined #glasgow
01:42
redstarcomrade has joined #glasgow
01:42
redstarcomrade has quit [Changing host]
01:42
redstarcomrade has joined #glasgow
01:58
notgull has quit [Ping timeout: 268 seconds]
03:35
FFY00 has joined #glasgow
03:35
FFY00_ has quit [Ping timeout: 272 seconds]
04:43
redstarcomrade has quit [Read error: Connection reset by peer]
09:16
fibmod has quit [Remote host closed the connection]
09:31
fibmod has joined #glasgow
09:39
fibmod has quit [Ping timeout: 268 seconds]
10:00
fibmod has joined #glasgow
10:02
galibert[m] has joined #glasgow
10:02
<
galibert[m] >
omnitechnomancer: usbip looks uniform accross OSes :-)
10:11
<
whitequark[cis] >
no usbip
10:12
<
galibert[m] >
huhuhu
10:12
<
galibert[m] >
How to summon Cat
10:45
fibmod has quit [Ping timeout: 255 seconds]
10:51
fibmod has joined #glasgow
11:41
fibmod has quit [Ping timeout: 264 seconds]
11:42
fibmod has joined #glasgow
11:51
bvernoux has joined #glasgow
14:05
vegard_e[m] has joined #glasgow
14:05
<
vegard_e[m] >
uniformly bad?
15:03
bvernoux has quit [Read error: Connection reset by peer]
15:04
bvernoux has joined #glasgow
15:25
redstarcomrade has joined #glasgow
16:12
redstarcomrade has quit [Read error: Connection reset by peer]
16:17
notgull has joined #glasgow
16:52
bvernoux_ has joined #glasgow
16:55
bvernoux has quit [Ping timeout: 240 seconds]
18:40
notgull has quit [Ping timeout: 246 seconds]
18:42
notgull has joined #glasgow
18:49
notgull has quit [Ping timeout: 246 seconds]
20:33
Foxyloxy has joined #glasgow
21:24
Foxyloxy has joined #glasgow
22:01
bvernoux_ has quit [Quit: Leaving]
22:04
Foxyloxy has joined #glasgow
23:06
sigstoat[m] has joined #glasgow
23:06
<
sigstoat[m] >
is there a way to feed a ClockGen from a specific signal? perhaps instantiate the submodule and then poke around inside of it somehow? my goal is to divide down the PLL, so i can get slower clocks than it will generate. (~1-3MHz)
23:35
itsmk has quit [Ping timeout: 264 seconds]
23:40
itsmk has joined #glasgow
23:44
<
Wanda[cis] >
create a clock domain with that signal as a clock, then use ClockGen with amaranth's DomainRenamer
23:49
<
sigstoat[m] >
oh i even looked at the renaming domains section of the docs and didn't put two and two together. thanks.