09:14 <fbrozovic> Hi guys, has anyone used the SPI controller with a peripheral that only supports mode 1 (CPOL 0 and CPHA 1)? I'm currently trying to interface to an ADS131M08 ADC and running into issues. If I simply set sck_idle to 0 and sck_edge to falling, the data is shifted out half a clock cycle too early...

09:15 <fbrozovic> I'm trying to fix the SPI controller to support mode 1 as well, but I'm unsure of the best way to do that

09:20 <whitequark> oh, oops, there might be bugs lurking in that code

09:27 <fbrozovic> is there an easy way to simulate the controller and write out a vcd file? so far i've been measuring the bus with a logic analyzer, but of course i have no visibility into the state of the controller like this, making it hard to debug

09:28 <whitequark> take a look at the unit tests that are present in some applets

10:05 <fbrozovic> looks like it might be enough to insert a delay of half an sck period between the RECV-DATA and TRANSFER states when CPHA=1. is there a better way to do that than simply counting sys_clk cycles?

10:15 <fbrozovic> scratch that, that just delays sck further