01:59 <d1b2> <ACCount> Found this thing online. Looks pretty cool - it implements a lot of the ideas I had for a similar device.

01:59 <d1b2> <ACCount> I wonder - is FX2 being USB 2.0 a meaningful bottleneck in any of the use cases?

02:01 <d1b2> <ACCount> When I wanted to build a high speed NAND dumper for myself, I went down the rabbit hole of USB 3 controllers.

02:03 <d1b2> <ACCount> Found some that are not utter unobtanium and don't cost more than the FPGA does.

02:04 <d1b2> <ACCount> As well as some significantly less sane USB 3 connectivity options.

02:04 <d1b2> <ACCount> Such as hacking a 3.0 MicroSD card reader into a general purpose USB interface IC.

02:18 <d1b2> <dragonmux> within the realm of the kinds of IO speeds you'll get from the FPGA, the USB HS interface is not a major bottle neck for the majority of applets

02:20 <d1b2> <dragonmux> under ideal conditions, the IO can be wiggled at about 50MHz, there are 16 IOs arranged in two banks of 8, and you can move 480Mb/s through the USB link for a benchmarked bandwidth of around 44MB/s.. that means you can either us about the full IO speed on one bank at a time, or about half on each bank at a time

02:21 <d1b2> <dragonmux> though it's not as simple as that and it doesn't have to be 1:1 as you can do a lot of processing on a bank's pins in gateware before the bytes created for/by the bank ever become something the USB interface needs to worry about

02:23 <whitequark> the IOs are banked only for power reasons; you can set the IO voltage for all pins in a bank as a group, not individually

02:23 <whitequark> how you organize data transfer is completely unrelated to banks

02:25 <d1b2> <dragonmux> sorry, yeah - we didn't mean to make it seem like the banks were related to data layout in any way

02:29 <whitequark> but yeah, this is otherwise correct: you can get the maximum USB 2 bulk bandwidth out of it easily if your host controller and OS allow it