17:44 <d1b2> <reps> someone who is definitely not me 😇 has soldered the FPGA on their c2 board the wrong way and powered it on https://i.imgur.com/A5K9lYC.jpg

17:44 <d1b2> <reps> now I think I've fixed it, but I am getting a "mode pins-int is broken on device revision C2" error in selftest ... does that mean all rev C2 boards or did I fry something after all? https://i.imgur.com/6QGuTNB.jpg

17:45 <gruetzkopf> that means all of them

17:45 <d1b2> <Attie> pins-int doesn't behave on revC

17:45 <d1b2> <Attie> see https://attie.co.uk/wiki/dev_boards/glasgow/

17:46 <gruetzkopf> glasgow in the way to less ppms?

17:46 <d1b2> <reps> ah that's good to know, thank you!

17:46 <d1b2> <Attie> np! if you pass the other tests, you should be set

17:47 <d1b2> <Attie> ("other" meaning as outlined on that link...)

17:52 <d1b2> <reps> will try right now! yeah I have a certain keithley 3706 switch mainframe with a firmware issue somewhere on its 2 dense, interconnected digital boards. no doubt many interfaces to explore ... so we'll see if this leads to ppms :ppmhub:

17:52 <d1b2> <Attie> ha, gl!

17:59 <gruetzkopf> looking forward to hearing about it!

18:00 <d1b2> <Attie> me too, let us know if you'd like any input

18:06 <d1b2> <reps> https://i.imgur.com/fBnUy63.jpg passed :success:

18:08 <d1b2> <Attie> nice! well done, glad it survived ☺️

21:08 <d1b2> <dragonmux> ooo, look forward to seeing the video about it

23:50 <d1b2> <xabean> congrats!