20:19 <d1b2> <tnt> So I want to turn if_clk into an output to make the Glagow the clock driver. Would class GlasgowHardwareTarget be the right place to stick all my clock/reset magic ?

20:19 <whitequark> yeah

20:20 <d1b2> <tnt> Tx.

20:20 <whitequark> I would normally warn about meeting timing on IO pads but you were the one who sorted that out in first place :)

20:20 <d1b2> <tnt> Yeah already looking at redoing the FX2 analysis for that case 😅

20:21 <whitequark> if the implementation is nice and clean I'd like to have that upstream as an option

20:21 <whitequark> maybe not generally advertised or used (though we'd need some ability to test it even in that case)

20:21 <whitequark> it was something I planned originally

20:23 <d1b2> <tnt> I figured that was the original plan since otherwise the way the pins are wired doesn't make any sense.

20:24 <whitequark> I did not have complete confidence in always driving the clock from the FX2, you see?

20:24 <whitequark> I wanted to have more options

20:24 <whitequark> actually hold on

20:24 <whitequark> if we always drive clk_if from the FPGA, we could always have both PLLs available for the applets, right?

20:25 <d1b2> <tnt> Yes. Although one of them would only have 1 output available.

20:25 <whitequark> yeah that's fine

20:25 <d1b2> <tnt> (since the other would be set to bypass)

20:41 <d1b2> <tnt> FX2 datasheet says """When using an external IFCLK, the external clock must be present before switching to the external clock with the IFCLKSRC bit.""" ... So what ... you're supposed to have the 2 drivers fight for a little bit while preparing ?

20:41 <whitequark> weird

20:43 <d1b2> <tnt> Oh there is a IFCLKOE bit I guess you're supposed to use that.

20:43 <whitequark> as far as I understand the FX2 FIFO block is clocked by IFCLK, so if that's absent you can't really do anything with it

20:43 <whitequark> never tested it on real hardware

20:44 <whitequark> but I imagine register writes would do nothing, etc

20:44 <whitequark> so you'd probably want to switch IFCLKSRC around loading the bitstream

20:44 <whitequark> this is an additional point of failure, but probably acceptable

20:47 <d1b2> <tnt> Yeah, fpga_start() looks like a good candidate but then also need to switch back to internal clock on fpga_reset or so since at that point the FPGA won't be providing a clock anymore.

20:47 <whitequark> yes